SCHM0103
|
SCHM0103
|
|
|
HEADER
|
HEADER
|
{
|
{
|
FREEID 1671
|
FREEID 1671
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#BLOCKTABLE_FILE="#table.bde"
|
#BLOCKTABLE_FILE="#table.bde"
|
#BLOCKTABLE_INCLUDED="1"
|
#BLOCKTABLE_INCLUDED="1"
|
#LANGUAGE="VERILOG"
|
#LANGUAGE="VERILOG"
|
#MODULE="forward2"
|
#MODULE="forward2"
|
AUTHOR="YlmF"
|
AUTHOR="YlmF"
|
COMPANY="WwW.YlmF.CoM"
|
COMPANY="WwW.YlmF.CoM"
|
CREATIONDATE="2008-8-10"
|
CREATIONDATE="2008-8-10"
|
TITLE="No Title"
|
TITLE="No Title"
|
}
|
}
|
SYMBOL "#default" "forward_node" "forward_node"
|
SYMBOL "#default" "forward_node" "forward_node"
|
{
|
{
|
HEADER
|
HEADER
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DESCRIPTION=""
|
#DESCRIPTION=""
|
#LANGUAGE="VERILOG"
|
#LANGUAGE="VERILOG"
|
#MODIFIED="1218305310"
|
#MODIFIED="1218305310"
|
}
|
}
|
}
|
}
|
PAGE ""
|
PAGE ""
|
{
|
{
|
PAGEHEADER
|
PAGEHEADER
|
{
|
{
|
RECT (0,0,320,240)
|
RECT (0,0,320,240)
|
FREEID 15
|
FREEID 15
|
}
|
}
|
|
|
BODY
|
BODY
|
{
|
{
|
RECT 1, -1, 0
|
RECT 1, -1, 0
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#OUTLINE_FILLING="1"
|
#OUTLINE_FILLING="1"
|
}
|
}
|
AREA (20,0,300,240)
|
AREA (20,0,300,240)
|
}
|
}
|
TEXT 3, 0, 0
|
TEXT 3, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,30,93,54)
|
RECT (25,30,93,54)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 2
|
PARENT 2
|
}
|
}
|
TEXT 5, 0, 0
|
TEXT 5, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (172,30,295,54)
|
RECT (172,30,295,54)
|
ALIGN 6
|
ALIGN 6
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 4
|
PARENT 4
|
}
|
}
|
TEXT 7, 0, 0
|
TEXT 7, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,70,181,94)
|
RECT (25,70,181,94)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 6
|
PARENT 6
|
}
|
}
|
TEXT 9, 0, 0
|
TEXT 9, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,110,93,134)
|
RECT (25,110,93,134)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 8
|
PARENT 8
|
}
|
}
|
TEXT 11, 0, 0
|
TEXT 11, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,150,181,174)
|
RECT (25,150,181,174)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 10
|
PARENT 10
|
}
|
}
|
TEXT 13, 0, 0
|
TEXT 13, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,190,104,214)
|
RECT (25,190,104,214)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 12
|
PARENT 12
|
}
|
}
|
PIN 2, 0, 0
|
PIN 2, 0, 0
|
{
|
{
|
COORD (0,40)
|
COORD (0,40)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="alu_we"
|
#NAME="alu_we"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
PIN 4, 0, 0
|
PIN 4, 0, 0
|
{
|
{
|
COORD (320,40)
|
COORD (320,40)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="OUT"
|
#DIRECTION="OUT"
|
#DOWNTO="1"
|
#DOWNTO="1"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="mux_fw(2:0)"
|
#NAME="mux_fw(2:0)"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (-20,0), (0,0) )
|
POINTS ( (-20,0), (0,0) )
|
}
|
}
|
}
|
}
|
PIN 6, 0, 0
|
PIN 6, 0, 0
|
{
|
{
|
COORD (0,80)
|
COORD (0,80)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#DOWNTO="1"
|
#DOWNTO="1"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="alu_wr_rn(4:0)"
|
#NAME="alu_wr_rn(4:0)"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
PIN 8, 0, 0
|
PIN 8, 0, 0
|
{
|
{
|
COORD (0,120)
|
COORD (0,120)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="mem_we"
|
#NAME="mem_we"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
PIN 10, 0, 0
|
PIN 10, 0, 0
|
{
|
{
|
COORD (0,160)
|
COORD (0,160)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#DOWNTO="1"
|
#DOWNTO="1"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="mem_wr_rn(4:0)"
|
#NAME="mem_wr_rn(4:0)"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
PIN 12, 0, 0
|
PIN 12, 0, 0
|
{
|
{
|
COORD (0,200)
|
COORD (0,200)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#DOWNTO="1"
|
#DOWNTO="1"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="rn(4:0)"
|
#NAME="rn(4:0)"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
SYMBOL "#default" "fw_latch5" "fw_latch5"
|
SYMBOL "#default" "fw_latch5" "fw_latch5"
|
{
|
{
|
HEADER
|
HEADER
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DESCRIPTION=""
|
#DESCRIPTION=""
|
#LANGUAGE="VERILOG"
|
#LANGUAGE="VERILOG"
|
#MODIFIED="1218305297"
|
#MODIFIED="1218305297"
|
}
|
}
|
}
|
}
|
PAGE ""
|
PAGE ""
|
{
|
{
|
PAGEHEADER
|
PAGEHEADER
|
{
|
{
|
RECT (0,0,160,120)
|
RECT (0,0,160,120)
|
FREEID 8
|
FREEID 8
|
}
|
}
|
|
|
BODY
|
BODY
|
{
|
{
|
RECT 1, -1, 0
|
RECT 1, -1, 0
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#OUTLINE_FILLING="1"
|
#OUTLINE_FILLING="1"
|
}
|
}
|
AREA (20,0,140,120)
|
AREA (20,0,140,120)
|
}
|
}
|
TEXT 3, 0, 0
|
TEXT 3, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,30,60,54)
|
RECT (25,30,60,54)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 2
|
PARENT 2
|
}
|
}
|
TEXT 5, 0, 0
|
TEXT 5, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (67,30,135,54)
|
RECT (67,30,135,54)
|
ALIGN 6
|
ALIGN 6
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 4
|
PARENT 4
|
}
|
}
|
TEXT 7, 0, 0
|
TEXT 7, 0, 0
|
{
|
{
|
TEXT "$#NAME"
|
TEXT "$#NAME"
|
RECT (25,70,93,94)
|
RECT (25,70,93,94)
|
ALIGN 4
|
ALIGN 4
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 6
|
PARENT 6
|
}
|
}
|
PIN 2, 0, 0
|
PIN 2, 0, 0
|
{
|
{
|
COORD (0,40)
|
COORD (0,40)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="clk"
|
#NAME="clk"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
PIN 4, 0, 0
|
PIN 4, 0, 0
|
{
|
{
|
COORD (160,40)
|
COORD (160,40)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="OUT"
|
#DIRECTION="OUT"
|
#DOWNTO="1"
|
#DOWNTO="1"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="q(4:0)"
|
#NAME="q(4:0)"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="reg"
|
#VERILOG_TYPE="reg"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (-20,0), (0,0) )
|
POINTS ( (-20,0), (0,0) )
|
}
|
}
|
}
|
}
|
PIN 6, 0, 0
|
PIN 6, 0, 0
|
{
|
{
|
COORD (0,80)
|
COORD (0,80)
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#DIRECTION="IN"
|
#DIRECTION="IN"
|
#DOWNTO="1"
|
#DOWNTO="1"
|
#LENGTH="20"
|
#LENGTH="20"
|
#MDA_RECORD_TOKEN="OTHER"
|
#MDA_RECORD_TOKEN="OTHER"
|
#NAME="d(4:0)"
|
#NAME="d(4:0)"
|
#NUMBER="0"
|
#NUMBER="0"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
LINE 2, 0, 0
|
LINE 2, 0, 0
|
{
|
{
|
POINTS ( (0,0), (20,0) )
|
POINTS ( (0,0), (20,0) )
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
PAGE ""
|
PAGE ""
|
{
|
{
|
PAGEHEADER
|
PAGEHEADER
|
{
|
{
|
PAGESIZE (3307,2338)
|
PAGESIZE (3307,2338)
|
MARGINS (200,200,200,200)
|
MARGINS (200,200,200,200)
|
RECT (0,0,100,200)
|
RECT (0,0,100,200)
|
}
|
}
|
|
|
BODY
|
BODY
|
{
|
{
|
INSTANCE 56, 0, 0
|
INSTANCE 56, 0, 0
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#COMPONENT="Input"
|
#COMPONENT="Input"
|
#LIBRARY="#terminals"
|
#LIBRARY="#terminals"
|
#REFERENCE="clk"
|
#REFERENCE="clk"
|
#SYMBOL="Input"
|
#SYMBOL="Input"
|
}
|
}
|
COORD (1180,1120)
|
COORD (1180,1120)
|
VERTEXES ( (2,1535) )
|
VERTEXES ( (2,1535) )
|
}
|
}
|
TEXT 57, 0, 0
|
TEXT 57, 0, 0
|
{
|
{
|
TEXT "$#REFERENCE"
|
TEXT "$#REFERENCE"
|
RECT (1076,1103,1129,1138)
|
RECT (1076,1103,1129,1138)
|
ALIGN 6
|
ALIGN 6
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 56
|
PARENT 56
|
}
|
}
|
INSTANCE 74, 0, 0
|
INSTANCE 74, 0, 0
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#COMPONENT="forward_node"
|
#COMPONENT="forward_node"
|
#LIBRARY="#default"
|
#LIBRARY="#default"
|
#REFERENCE="fw_alu_rs"
|
#REFERENCE="fw_alu_rs"
|
#SYMBOL="forward_node"
|
#SYMBOL="forward_node"
|
}
|
}
|
COORD (1640,400)
|
COORD (1640,400)
|
VERTEXES ( (2,1491), (6,1500), (8,1506), (10,1510), (12,1486), (4,1518) )
|
VERTEXES ( (2,1491), (6,1500), (8,1506), (10,1510), (12,1486), (4,1518) )
|
}
|
}
|
TEXT 76, 0, 0
|
TEXT 76, 0, 0
|
{
|
{
|
TEXT "$#REFERENCE"
|
TEXT "$#REFERENCE"
|
RECT (1640,364,1795,399)
|
RECT (1640,364,1795,399)
|
ALIGN 8
|
ALIGN 8
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 74
|
PARENT 74
|
}
|
}
|
TEXT 77, 0, 0
|
TEXT 77, 0, 0
|
{
|
{
|
TEXT "$#COMPONENT"
|
TEXT "$#COMPONENT"
|
RECT (1640,640,1846,675)
|
RECT (1640,640,1846,675)
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 74
|
PARENT 74
|
}
|
}
|
INSTANCE 78, 0, 0
|
INSTANCE 78, 0, 0
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#COMPONENT="fw_latch5"
|
#COMPONENT="fw_latch5"
|
#LIBRARY="#default"
|
#LIBRARY="#default"
|
#REFERENCE="fw_reg_rns"
|
#REFERENCE="fw_reg_rns"
|
#SYMBOL="fw_latch5"
|
#SYMBOL="fw_latch5"
|
}
|
}
|
COORD (1360,560)
|
COORD (1360,560)
|
VERTEXES ( (2,1489), (6,1513), (4,1487) )
|
VERTEXES ( (2,1489), (6,1513), (4,1487) )
|
}
|
}
|
TEXT 80, 0, 0
|
TEXT 80, 0, 0
|
{
|
{
|
TEXT "$#REFERENCE"
|
TEXT "$#REFERENCE"
|
RECT (1360,524,1532,559)
|
RECT (1360,524,1532,559)
|
ALIGN 8
|
ALIGN 8
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 78
|
PARENT 78
|
}
|
}
|
TEXT 81, 0, 0
|
TEXT 81, 0, 0
|
{
|
{
|
TEXT "$#COMPONENT"
|
TEXT "$#COMPONENT"
|
RECT (1360,680,1515,715)
|
RECT (1360,680,1515,715)
|
MARGINS (1,1)
|
MARGINS (1,1)
|
PARENT 78
|
PARENT 78
|
}
|
}
|
NET BUS 82, 0, 0
|
NET BUS 82, 0, 0
|
INSTANCE 94, 0, 0
|
INSTANCE 94, 0, 0
|
{
|
{
|
VARIABLES
|
VARIABLES
|
{
|
{
|
#COMPONENT="forward_node"
|
#COMPONENT="forward_node"
|
#LIBRARY="#default"
|
#LIBRARY="#default"
|
#REFERENCE="fw_cmp_rs"
|
#REFERENCE="fw_cmp_rs"
|
#SYMBOL="forward_node"
|
#SYMBOL="forward_node"
|
}
|
}
|
COORD (1640,700)
|
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{
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|
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|
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|
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|
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COORD (1640,1340)
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INSTANCE 303, 0, 0
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|
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INSTANCE 359, 0, 0
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{
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|
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PARENT 359
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PARENT 359
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}
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NET WIRE 410, 0, 0
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NET WIRE 410, 0, 0
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NET BUS 447, 0, 0
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NET BUS 447, 0, 0
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NET WIRE 472, 0, 0
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NET WIRE 472, 0, 0
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NET BUS 550, 0, 0
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NET BUS 550, 0, 0
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NET BUS 559, 0, 0
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|
#REFERENCE="alu_rt_fw(2:0)"
|
#SYMBOL="BusOutput"
|
#SYMBOL="BusOutput"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
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TEXT "$#REFERENCE"
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RECT (2112,1043,2352,1078)
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INSTANCE 606, 0, 0
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INSTANCE 606, 0, 0
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{
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VARIABLES
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{
|
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|
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|
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|
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|
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|
#REFERENCE="cmp_rs_fw(2:0)"
|
#SYMBOL="BusOutput"
|
#SYMBOL="BusOutput"
|
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|
#VERILOG_TYPE="wire"
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COORD (2060,740)
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COORD (2060,740)
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PARENT 606
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INSTANCE 615, 0, 0
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INSTANCE 615, 0, 0
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{
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VARIABLES
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VARIABLES
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{
|
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|
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|
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|
#LIBRARY="#terminals"
|
#REFERENCE="cmp_rt_fw(2:0)"
|
#REFERENCE="cmp_rt_fw(2:0)"
|
#SYMBOL="BusOutput"
|
#SYMBOL="BusOutput"
|
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#VERILOG_TYPE="wire"
|
}
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COORD (2040,1380)
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COORD (2040,1380)
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{
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TEXT "$#REFERENCE"
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ALIGN 4
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MARGINS (1,1)
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MARGINS (1,1)
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PARENT 615
|
PARENT 615
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}
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}
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NET BUS 620, 0, 0
|
NET BUS 620, 0, 0
|
INSTANCE 624, 0, 0
|
INSTANCE 624, 0, 0
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{
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{
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VARIABLES
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VARIABLES
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{
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{
|
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|
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|
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|
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|
#REFERENCE="dmem_fw(2:0)"
|
#REFERENCE="dmem_fw(2:0)"
|
#SYMBOL="BusOutput"
|
#SYMBOL="BusOutput"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
}
|
}
|
COORD (2060,1200)
|
COORD (2060,1200)
|
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|
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{
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TEXT "$#REFERENCE"
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RECT (2112,1183,2318,1218)
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|
MARGINS (1,1)
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PARENT 624
|
PARENT 624
|
}
|
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|
INSTANCE 633, 0, 0
|
INSTANCE 633, 0, 0
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{
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{
|
VARIABLES
|
VARIABLES
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{
|
{
|
#COMPONENT="BusOutput"
|
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|
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|
#LIBRARY="#terminals"
|
#REFERENCE="alu_rs_fw(2:0)"
|
#REFERENCE="alu_rs_fw(2:0)"
|
#SYMBOL="BusOutput"
|
#SYMBOL="BusOutput"
|
#VERILOG_TYPE="wire"
|
#VERILOG_TYPE="wire"
|
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|
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COORD (2040,440)
|
COORD (2040,440)
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TEXT 634, 0, 0
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{
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{
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TEXT "$#REFERENCE"
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ALIGN 4
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MARGINS (1,1)
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PARENT 633
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PARENT 633
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|
NET BUS 635, 0, 0
|
NET BUS 635, 0, 0
|
NET BUS 937, 0, 0
|
NET BUS 937, 0, 0
|
NET BUS 1100, 0, 0
|
NET BUS 1100, 0, 0
|
NET BUS 1163, 0, 0
|
NET BUS 1163, 0, 0
|
NET WIRE 1175, 0, 0
|
NET WIRE 1175, 0, 0
|
NET BUS 1345, 0, 0
|
NET BUS 1345, 0, 0
|
VTX 1486, 0, 0
|
VTX 1486, 0, 0
|
{
|
{
|
COORD (1640,600)
|
COORD (1640,600)
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}
|
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VTX 1487, 0, 0
|
VTX 1487, 0, 0
|
{
|
{
|
COORD (1520,600)
|
COORD (1520,600)
|
}
|
}
|
VTX 1488, 0, 0
|
VTX 1488, 0, 0
|
{
|
{
|
COORD (1340,1120)
|
COORD (1340,1120)
|
}
|
}
|
VTX 1489, 0, 0
|
VTX 1489, 0, 0
|
{
|
{
|
COORD (1360,600)
|
COORD (1360,600)
|
}
|
}
|
VTX 1490, 0, 0
|
VTX 1490, 0, 0
|
{
|
{
|
COORD (1360,1220)
|
COORD (1360,1220)
|
}
|
}
|
VTX 1491, 0, 0
|
VTX 1491, 0, 0
|
{
|
{
|
COORD (1640,440)
|
COORD (1640,440)
|
}
|
}
|
VTX 1492, 0, 0
|
VTX 1492, 0, 0
|
{
|
{
|
COORD (1300,740)
|
COORD (1300,740)
|
}
|
}
|
VTX 1493, 0, 0
|
VTX 1493, 0, 0
|
{
|
{
|
COORD (1640,740)
|
COORD (1640,740)
|
}
|
}
|
VTX 1494, 0, 0
|
VTX 1494, 0, 0
|
{
|
{
|
COORD (1460,740)
|
COORD (1460,740)
|
}
|
}
|
VTX 1495, 0, 0
|
VTX 1495, 0, 0
|
{
|
{
|
COORD (1580,1060)
|
COORD (1580,1060)
|
}
|
}
|
VTX 1496, 0, 0
|
VTX 1496, 0, 0
|
{
|
{
|
COORD (1640,1060)
|
COORD (1640,1060)
|
}
|
}
|
VTX 1497, 0, 0
|
VTX 1497, 0, 0
|
{
|
{
|
COORD (1640,1380)
|
COORD (1640,1380)
|
}
|
}
|
VTX 1498, 0, 0
|
VTX 1498, 0, 0
|
{
|
{
|
COORD (1560,780)
|
COORD (1560,780)
|
}
|
}
|
VTX 1499, 0, 0
|
VTX 1499, 0, 0
|
{
|
{
|
COORD (1640,780)
|
COORD (1640,780)
|
}
|
}
|
VTX 1500, 0, 0
|
VTX 1500, 0, 0
|
{
|
{
|
COORD (1640,480)
|
COORD (1640,480)
|
}
|
}
|
VTX 1501, 0, 0
|
VTX 1501, 0, 0
|
{
|
{
|
COORD (1640,1100)
|
COORD (1640,1100)
|
}
|
}
|
VTX 1502, 0, 0
|
VTX 1502, 0, 0
|
{
|
{
|
COORD (1560,1100)
|
COORD (1560,1100)
|
}
|
}
|
VTX 1503, 0, 0
|
VTX 1503, 0, 0
|
{
|
{
|
COORD (1640,1420)
|
COORD (1640,1420)
|
}
|
}
|
VTX 1504, 0, 0
|
VTX 1504, 0, 0
|
{
|
{
|
COORD (1600,820)
|
COORD (1600,820)
|
}
|
}
|
VTX 1505, 0, 0
|
VTX 1505, 0, 0
|
{
|
{
|
COORD (1640,820)
|
COORD (1640,820)
|
}
|
}
|
VTX 1506, 0, 0
|
VTX 1506, 0, 0
|
{
|
{
|
COORD (1640,520)
|
COORD (1640,520)
|
}
|
}
|
VTX 1507, 0, 0
|
VTX 1507, 0, 0
|
{
|
{
|
COORD (1640,1140)
|
COORD (1640,1140)
|
}
|
}
|
VTX 1508, 0, 0
|
VTX 1508, 0, 0
|
{
|
{
|
COORD (1600,1140)
|
COORD (1600,1140)
|
}
|
}
|
VTX 1509, 0, 0
|
VTX 1509, 0, 0
|
{
|
{
|
COORD (1640,1460)
|
COORD (1640,1460)
|
}
|
}
|
VTX 1510, 0, 0
|
VTX 1510, 0, 0
|
{
|
{
|
COORD (1640,560)
|
COORD (1640,560)
|
}
|
}
|
VTX 1511, 0, 0
|
VTX 1511, 0, 0
|
{
|
{
|
COORD (1540,860)
|
COORD (1540,860)
|
}
|
}
|
VTX 1512, 0, 0
|
VTX 1512, 0, 0
|
{
|
{
|
COORD (1640,860)
|
COORD (1640,860)
|
}
|
}
|
VTX 1513, 0, 0
|
VTX 1513, 0, 0
|
{
|
{
|
COORD (1360,640)
|
COORD (1360,640)
|
}
|
}
|
VTX 1514, 0, 0
|
VTX 1514, 0, 0
|
{
|
{
|
COORD (1320,640)
|
COORD (1320,640)
|
}
|
}
|
VTX 1515, 0, 0
|
VTX 1515, 0, 0
|
{
|
{
|
COORD (1360,1260)
|
COORD (1360,1260)
|
}
|
}
|
VTX 1516, 0, 0
|
VTX 1516, 0, 0
|
{
|
{
|
COORD (1340,1260)
|
COORD (1340,1260)
|
}
|
}
|
VTX 1517, 0, 0
|
VTX 1517, 0, 0
|
{
|
{
|
COORD (1640,1540)
|
COORD (1640,1540)
|
}
|
}
|
VTX 1518, 0, 0
|
VTX 1518, 0, 0
|
{
|
{
|
COORD (1960,440)
|
COORD (1960,440)
|
}
|
}
|
VTX 1519, 0, 0
|
VTX 1519, 0, 0
|
{
|
{
|
COORD (2040,440)
|
COORD (2040,440)
|
}
|
}
|
VTX 1520, 0, 0
|
VTX 1520, 0, 0
|
{
|
{
|
COORD (1960,1380)
|
COORD (1960,1380)
|
}
|
}
|
VTX 1521, 0, 0
|
VTX 1521, 0, 0
|
{
|
{
|
COORD (2040,1380)
|
COORD (2040,1380)
|
}
|
}
|
VTX 1522, 0, 0
|
VTX 1522, 0, 0
|
{
|
{
|
COORD (1180,640)
|
COORD (1180,640)
|
}
|
}
|
VTX 1523, 0, 0
|
VTX 1523, 0, 0
|
{
|
{
|
COORD (1180,740)
|
COORD (1180,740)
|
}
|
}
|
VTX 1524, 0, 0
|
VTX 1524, 0, 0
|
{
|
{
|
COORD (1180,1260)
|
COORD (1180,1260)
|
}
|
}
|
VTX 1525, 0, 0
|
VTX 1525, 0, 0
|
{
|
{
|
COORD (1540,980)
|
COORD (1540,980)
|
}
|
}
|
VTX 1526, 0, 0
|
VTX 1526, 0, 0
|
{
|
{
|
COORD (1640,1180)
|
COORD (1640,1180)
|
}
|
}
|
VTX 1527, 0, 0
|
VTX 1527, 0, 0
|
{
|
{
|
COORD (1180,820)
|
COORD (1180,820)
|
}
|
}
|
VTX 1528, 0, 0
|
VTX 1528, 0, 0
|
{
|
{
|
COORD (1180,780)
|
COORD (1180,780)
|
}
|
}
|
VTX 1529, 0, 0
|
VTX 1529, 0, 0
|
{
|
{
|
COORD (1180,980)
|
COORD (1180,980)
|
}
|
}
|
VTX 1530, 0, 0
|
VTX 1530, 0, 0
|
{
|
{
|
COORD (1300,980)
|
COORD (1300,980)
|
}
|
}
|
VTX 1531, 0, 0
|
VTX 1531, 0, 0
|
{
|
{
|
COORD (1640,1500)
|
COORD (1640,1500)
|
}
|
}
|
VTX 1532, 0, 0
|
VTX 1532, 0, 0
|
{
|
{
|
COORD (1640,900)
|
COORD (1640,900)
|
}
|
}
|
VTX 1533, 0, 0
|
VTX 1533, 0, 0
|
{
|
{
|
COORD (2060,740)
|
COORD (2060,740)
|
}
|
}
|
VTX 1534, 0, 0
|
VTX 1534, 0, 0
|
{
|
{
|
COORD (1960,740)
|
COORD (1960,740)
|
}
|
}
|
VTX 1535, 0, 0
|
VTX 1535, 0, 0
|
{
|
{
|
COORD (1180,1120)
|
COORD (1180,1120)
|
}
|
}
|
VTX 1536, 0, 0
|
VTX 1536, 0, 0
|
{
|
{
|
COORD (1640,1220)
|
COORD (1640,1220)
|
}
|
}
|
VTX 1537, 0, 0
|
VTX 1537, 0, 0
|
{
|
{
|
COORD (1520,1220)
|
COORD (1520,1220)
|
}
|
}
|
VTX 1538, 0, 0
|
VTX 1538, 0, 0
|
{
|
{
|
COORD (2060,1060)
|
COORD (2060,1060)
|
}
|
}
|
VTX 1539, 0, 0
|
VTX 1539, 0, 0
|
{
|
{
|
COORD (2020,1060)
|
COORD (2020,1060)
|
}
|
}
|
VTX 1540, 0, 0
|
VTX 1540, 0, 0
|
{
|
{
|
COORD (1960,1060)
|
COORD (1960,1060)
|
}
|
}
|
VTX 1541, 0, 0
|
VTX 1541, 0, 0
|
{
|
{
|
COORD (2060,1200)
|
COORD (2060,1200)
|
}
|
}
|
BUS 1542, 0, 0
|
BUS 1542, 0, 0
|
{
|
{
|
NET 82
|
NET 82
|
VTX 1486, 1487
|
VTX 1486, 1487
|
}
|
}
|
VTX 1543, 0, 0
|
VTX 1543, 0, 0
|
{
|
{
|
COORD (1340,600)
|
COORD (1340,600)
|
}
|
}
|
WIRE 1544, 0, 0
|
WIRE 1544, 0, 0
|
{
|
{
|
NET 1175
|
NET 1175
|
VTX 1488, 1543
|
VTX 1488, 1543
|
}
|
}
|
WIRE 1545, 0, 0
|
WIRE 1545, 0, 0
|
{
|
{
|
NET 1175
|
NET 1175
|
VTX 1543, 1489
|
VTX 1543, 1489
|
}
|
}
|
VTX 1546, 0, 0
|
VTX 1546, 0, 0
|
{
|
{
|
COORD (1340,1220)
|
COORD (1340,1220)
|
}
|
}
|
WIRE 1547, 0, 0
|
WIRE 1547, 0, 0
|
{
|
{
|
NET 1175
|
NET 1175
|
VTX 1488, 1546
|
VTX 1488, 1546
|
}
|
}
|
WIRE 1548, 0, 0
|
WIRE 1548, 0, 0
|
{
|
{
|
NET 1175
|
NET 1175
|
VTX 1546, 1490
|
VTX 1546, 1490
|
}
|
}
|
VTX 1549, 0, 0
|
VTX 1549, 0, 0
|
{
|
{
|
COORD (1300,440)
|
COORD (1300,440)
|
}
|
}
|
WIRE 1550, 0, 0
|
WIRE 1550, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1491, 1549
|
VTX 1491, 1549
|
}
|
}
|
WIRE 1551, 0, 0
|
WIRE 1551, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1549, 1492
|
VTX 1549, 1492
|
}
|
}
|
WIRE 1552, 0, 0
|
WIRE 1552, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1493, 1494
|
VTX 1493, 1494
|
}
|
}
|
WIRE 1553, 0, 0
|
WIRE 1553, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1494, 1492
|
VTX 1494, 1492
|
}
|
}
|
VTX 1554, 0, 0
|
VTX 1554, 0, 0
|
{
|
{
|
COORD (1460,1060)
|
COORD (1460,1060)
|
}
|
}
|
WIRE 1555, 0, 0
|
WIRE 1555, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1494, 1554
|
VTX 1494, 1554
|
}
|
}
|
WIRE 1556, 0, 0
|
WIRE 1556, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1554, 1495
|
VTX 1554, 1495
|
}
|
}
|
WIRE 1557, 0, 0
|
WIRE 1557, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1495, 1496
|
VTX 1495, 1496
|
}
|
}
|
VTX 1558, 0, 0
|
VTX 1558, 0, 0
|
{
|
{
|
COORD (1580,1380)
|
COORD (1580,1380)
|
}
|
}
|
WIRE 1559, 0, 0
|
WIRE 1559, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1495, 1558
|
VTX 1495, 1558
|
}
|
}
|
WIRE 1560, 0, 0
|
WIRE 1560, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1558, 1497
|
VTX 1558, 1497
|
}
|
}
|
BUS 1561, 0, 0
|
BUS 1561, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1498, 1499
|
VTX 1498, 1499
|
}
|
}
|
VTX 1562, 0, 0
|
VTX 1562, 0, 0
|
{
|
{
|
COORD (1560,480)
|
COORD (1560,480)
|
}
|
}
|
BUS 1563, 0, 0
|
BUS 1563, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1500, 1562
|
VTX 1500, 1562
|
}
|
}
|
BUS 1564, 0, 0
|
BUS 1564, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1562, 1498
|
VTX 1562, 1498
|
}
|
}
|
BUS 1565, 0, 0
|
BUS 1565, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1501, 1502
|
VTX 1501, 1502
|
}
|
}
|
BUS 1566, 0, 0
|
BUS 1566, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1502, 1498
|
VTX 1502, 1498
|
}
|
}
|
VTX 1567, 0, 0
|
VTX 1567, 0, 0
|
{
|
{
|
COORD (1560,1420)
|
COORD (1560,1420)
|
}
|
}
|
BUS 1568, 0, 0
|
BUS 1568, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1503, 1567
|
VTX 1503, 1567
|
}
|
}
|
BUS 1569, 0, 0
|
BUS 1569, 0, 0
|
{
|
{
|
NET 447
|
NET 447
|
VTX 1567, 1502
|
VTX 1567, 1502
|
}
|
}
|
WIRE 1570, 0, 0
|
WIRE 1570, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1504, 1505
|
VTX 1504, 1505
|
}
|
}
|
VTX 1571, 0, 0
|
VTX 1571, 0, 0
|
{
|
{
|
COORD (1600,520)
|
COORD (1600,520)
|
}
|
}
|
WIRE 1572, 0, 0
|
WIRE 1572, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1506, 1571
|
VTX 1506, 1571
|
}
|
}
|
WIRE 1573, 0, 0
|
WIRE 1573, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1571, 1504
|
VTX 1571, 1504
|
}
|
}
|
WIRE 1574, 0, 0
|
WIRE 1574, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1507, 1508
|
VTX 1507, 1508
|
}
|
}
|
WIRE 1575, 0, 0
|
WIRE 1575, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1508, 1504
|
VTX 1508, 1504
|
}
|
}
|
VTX 1576, 0, 0
|
VTX 1576, 0, 0
|
{
|
{
|
COORD (1600,1460)
|
COORD (1600,1460)
|
}
|
}
|
WIRE 1577, 0, 0
|
WIRE 1577, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1508, 1576
|
VTX 1508, 1576
|
}
|
}
|
WIRE 1578, 0, 0
|
WIRE 1578, 0, 0
|
{
|
{
|
NET 472
|
NET 472
|
VTX 1576, 1509
|
VTX 1576, 1509
|
}
|
}
|
VTX 1579, 0, 0
|
VTX 1579, 0, 0
|
{
|
{
|
COORD (1540,560)
|
COORD (1540,560)
|
}
|
}
|
BUS 1580, 0, 0
|
BUS 1580, 0, 0
|
{
|
{
|
NET 1100
|
NET 1100
|
VTX 1510, 1579
|
VTX 1510, 1579
|
}
|
}
|
BUS 1581, 0, 0
|
BUS 1581, 0, 0
|
{
|
{
|
NET 1100
|
NET 1100
|
VTX 1579, 1511
|
VTX 1579, 1511
|
}
|
}
|
BUS 1582, 0, 0
|
BUS 1582, 0, 0
|
{
|
{
|
NET 1100
|
NET 1100
|
VTX 1512, 1511
|
VTX 1512, 1511
|
}
|
}
|
BUS 1583, 0, 0
|
BUS 1583, 0, 0
|
{
|
{
|
NET 550
|
NET 550
|
VTX 1513, 1514
|
VTX 1513, 1514
|
}
|
}
|
BUS 1584, 0, 0
|
BUS 1584, 0, 0
|
{
|
{
|
NET 559
|
NET 559
|
VTX 1515, 1516
|
VTX 1515, 1516
|
}
|
}
|
VTX 1585, 0, 0
|
VTX 1585, 0, 0
|
{
|
{
|
COORD (1340,1540)
|
COORD (1340,1540)
|
}
|
}
|
BUS 1586, 0, 0
|
BUS 1586, 0, 0
|
{
|
{
|
NET 559
|
NET 559
|
VTX 1516, 1585
|
VTX 1516, 1585
|
}
|
}
|
BUS 1587, 0, 0
|
BUS 1587, 0, 0
|
{
|
{
|
NET 559
|
NET 559
|
VTX 1585, 1517
|
VTX 1585, 1517
|
}
|
}
|
BUS 1588, 0, 0
|
BUS 1588, 0, 0
|
{
|
{
|
NET 635
|
NET 635
|
VTX 1518, 1519
|
VTX 1518, 1519
|
}
|
}
|
BUS 1589, 0, 0
|
BUS 1589, 0, 0
|
{
|
{
|
NET 620
|
NET 620
|
VTX 1520, 1521
|
VTX 1520, 1521
|
}
|
}
|
BUS 1590, 0, 0
|
BUS 1590, 0, 0
|
{
|
{
|
NET 550
|
NET 550
|
VTX 1514, 1522
|
VTX 1514, 1522
|
}
|
}
|
WIRE 1591, 0, 0
|
WIRE 1591, 0, 0
|
{
|
{
|
NET 410
|
NET 410
|
VTX 1492, 1523
|
VTX 1492, 1523
|
}
|
}
|
BUS 1592, 0, 0
|
BUS 1592, 0, 0
|
{
|
{
|
NET 559
|
NET 559
|
VTX 1516, 1524
|
VTX 1516, 1524
|
}
|
}
|
VTX 1593, 0, 0
|
VTX 1593, 0, 0
|
{
|
{
|
COORD (1540,1180)
|
COORD (1540,1180)
|
}
|
}
|
BUS 1594, 0, 0
|
BUS 1594, 0, 0
|
{
|
{
|
NET 1100
|
NET 1100
|
VTX 1525, 1593
|
VTX 1525, 1593
|
}
|
}
|
BUS 1595, 0, 0
|
BUS 1595, 0, 0
|
{
|
{
|
NET 1100
|
NET 1100
|
VTX 1593, 1526
|
VTX 1593, 1526
|
}
|
}
|
WIRE 1596, 0, 0
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