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| Rev 4 |
Rev 51 |
`define SEG7LED_ADDR 'H80_00_00_10
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`define SEG7LED_ADDR 'H80_00_00_10
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`define DMEM_SB 1
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`define DMEM_SB 1
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module mips_seg7led (
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module mips_seg7led (
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input [31:0] addr_i,
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input [31:0] addr_i,
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input clk,
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input clk,
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input [31:0] din,
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input [31:0] din,
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input [3:0]dmem_ctl_i,
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input [3:0]dmem_ctl_i,
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input rst,
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input rst,
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output [6:0]seg7led1,
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output [6:0]seg7led1,
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output [6:0]seg7led2
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output [6:0]seg7led2
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);
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);
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reg [7:0] data;
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reg [7:0] data;
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wire wr_seg7led;
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wire wr_seg7led;
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assign wr_seg7led= (addr_i==`SEG7LED_ADDR)&&(dmem_ctl_i==`DMEM_SB ) ;
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assign wr_seg7led= (addr_i==`SEG7LED_ADDR)&&(dmem_ctl_i==`DMEM_SB ) ;
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always @(posedge clk)
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always @(posedge clk)
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if (wr_seg7led)
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if (wr_seg7led)
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data<=din[7:0]; //no matter big-endian or little
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data<=din[7:0]; //no matter big-endian or little
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assign seg7led1= seg(data[3:0]) ;
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assign seg7led1= seg(data[3:0]) ;
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assign seg7led2= seg(data[7:4]) ;
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assign seg7led2= seg(data[7:4]) ;
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function [7:0] seg;
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function [7:0] seg;
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input [3:0] addr;
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input [3:0] addr;
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begin
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begin
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case(addr)
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case(addr)
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0: seg = 7'b0111111;
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0: seg = 7'b0111111;
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1: seg = 7'b0000110;
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1: seg = 7'b0000110;
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2: seg = 7'b1011011;
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2: seg = 7'b1011011;
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3: seg = 7'b1001111;
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3: seg = 7'b1001111;
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4: seg = 7'b1100110;
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4: seg = 7'b1100110;
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5: seg = 7'b1101101;
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5: seg = 7'b1101101;
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6: seg = 7'b1111100;
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6: seg = 7'b1111100;
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7: seg = 7'b0000111;
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7: seg = 7'b0000111;
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8: seg = 7'b1111111;
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8: seg = 7'b1111111;
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9: seg = 7'b1100111;
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9: seg = 7'b1100111;
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10: seg = 7'b1110111;
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10: seg = 7'b1110111;
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11: seg = 7'b1111100;
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11: seg = 7'b1111100;
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12: seg = 7'b1011000;
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12: seg = 7'b1011000;
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13: seg = 7'b1011110;
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13: seg = 7'b1011110;
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14: seg = 7'b1111001;
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14: seg = 7'b1111001;
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15: seg = 7'b1110001;
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15: seg = 7'b1110001;
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default: seg = {7{1'b0}};
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default: seg = {7{1'b0}};
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endcase
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endcase
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end
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end
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endfunction
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endfunction
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