/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// Author: Liwei ////
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//// Author: Liwei ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// If you encountered any problem, please contact : ////
|
//// If you encountered any problem, please contact : ////
|
//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// ////
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//// ////
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//// Downloaded from: ////
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//// Downloaded from: ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// mcupro@yahoo.com.hk ////
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//// mcupro@yahoo.com.hk ////
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//// ////
|
//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed freely without ////
|
//// This source file may be used and distributed freely without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and any derivative work contains the ////
|
//// removed from the file and any derivative work contains the ////
|
//// original copyright notice and the associated disclaimer. ////
|
//// original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// Please let the author know if it is used ////
|
//// Please let the author know if it is used ////
|
//// for commercial purpose. ////
|
//// for commercial purpose. ////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Date of Creation: 2007.8.1 ////
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//// Date of Creation: 2007.8.1 ////
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//// ////
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//// ////
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//// Version: 0.0.1 ////
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//// Version: 0.0.1 ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// ////
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//// ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Change log: ////
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//// Change log: ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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module ctl_FSM8 (
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module ctl_FSM8 (
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clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
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clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
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id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
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id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
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pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
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pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
|
);
|
);
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|
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parameter
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parameter
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ID_CUR = 1,
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ID_CUR = 1,
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ID_LD = 5,
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ID_LD = 5,
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ID_MUL = 2,
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ID_MUL = 2,
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ID_NOI = 6,
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ID_NOI = 6,
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ID_RET = 4,
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ID_RET = 4,
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ONE = 1,
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ONE = 1,
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PC_IGN = 1,
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PC_IGN = 1,
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PC_IRQ = 4,
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PC_IRQ = 4,
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PC_KEP = 2,
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PC_KEP = 2,
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PC_RST = 8,
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PC_RST = 8,
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ZERO = 0;
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ZERO = 0;
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input clk;
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input clk;
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input [2:0] id_cmd;
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input [2:0] id_cmd;
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input irq;
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input irq;
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input rst;
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input rst;
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output iack;
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output iack;
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output zz_is_nop;
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output zz_is_nop;
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output id2ra_ctl_clr;
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output id2ra_ctl_clr;
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output id2ra_ctl_cls;
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output id2ra_ctl_cls;
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output id2ra_ins_clr;
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output id2ra_ins_clr;
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output id2ra_ins_cls;
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output id2ra_ins_cls;
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output [3:0] pc_prectl;
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output [3:0] pc_prectl;
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output ra2exec_ctl_clr;
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output ra2exec_ctl_clr;
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wire clk;
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wire clk;
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reg iack;
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reg iack;
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reg zz_is_nop;
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reg zz_is_nop;
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reg id2ra_ctl_clr;
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reg id2ra_ctl_clr;
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reg id2ra_ctl_cls;
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reg id2ra_ctl_cls;
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reg id2ra_ins_clr;
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reg id2ra_ins_clr;
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reg id2ra_ins_cls;
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reg id2ra_ins_cls;
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wire [2:0] id_cmd;
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wire [2:0] id_cmd;
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wire irq;
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wire irq;
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reg [3:0] pc_prectl;
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reg [3:0] pc_prectl;
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reg ra2exec_ctl_clr;
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reg ra2exec_ctl_clr;
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wire rst;
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wire rst;
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reg [0:5]delay_counter_Sreg0, next_delay_counter_Sreg0;
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reg [0:5]delay_counter_Sreg0, next_delay_counter_Sreg0;
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`define D2_MUL_DLY 4'b0000
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`define D2_MUL_DLY 4'b0000
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`define IDLE 4'b0001
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`define IDLE 4'b0001
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`define MUL 4'b0010
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`define MUL 4'b0010
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`define CUR 4'b0011
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`define CUR 4'b0011
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`define RET 4'b0100
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`define RET 4'b0100
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`define IRQ 4'b0101
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`define IRQ 4'b0101
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`define RST 4'b0110
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`define RST 4'b0110
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`define LD 4'b0111
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`define LD 4'b0111
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`define NOI 4'b1000
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`define NOI 4'b1000
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reg [3:0] CurrState_Sreg0;
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reg [3:0] CurrState_Sreg0;
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reg [3:0] NextState_Sreg0;
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reg [3:0] NextState_Sreg0;
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reg riack;
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reg riack;
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always @ (*)
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always @ (*)
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begin : Sreg0_NextState
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begin : Sreg0_NextState
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case (CurrState_Sreg0) // synopsys parallel_case full_case
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case (CurrState_Sreg0) // synopsys parallel_case full_case
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`IDLE:
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`IDLE:
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begin
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begin
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id2ra_ins_clr=ZERO;
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id2ra_ins_clr=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr =ZERO;
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ra2exec_ctl_clr =ZERO;
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pc_prectl=PC_IGN;
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pc_prectl=PC_IGN;
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iack = riack;
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iack = riack;
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if ((irq)&&(~iack))
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if ((irq)&&(~iack))
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NextState_Sreg0 <= `IRQ;
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NextState_Sreg0 <= `IRQ;
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else if (id_cmd ==ID_NOI)
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else if (id_cmd ==ID_NOI)
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NextState_Sreg0 <= `NOI;
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NextState_Sreg0 <= `NOI;
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else if (id_cmd==ID_CUR)
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else if (id_cmd==ID_CUR)
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NextState_Sreg0 <= `CUR;
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NextState_Sreg0 <= `CUR;
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else if (id_cmd==ID_MUL)
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else if (id_cmd==ID_MUL)
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NextState_Sreg0 <= `MUL;
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NextState_Sreg0 <= `MUL;
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else if (id_cmd==ID_LD)
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else if (id_cmd==ID_LD)
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NextState_Sreg0 <= `LD;
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NextState_Sreg0 <= `LD;
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else if (id_cmd==ID_RET)
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else if (id_cmd==ID_RET)
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NextState_Sreg0 <= `RET;
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NextState_Sreg0 <= `RET;
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else
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else
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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end
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end
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`MUL:
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`MUL:
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begin
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begin
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id2ra_ins_clr=ONE;
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id2ra_ins_clr=ONE;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr=ZERO;
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ra2exec_ctl_clr=ZERO;
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pc_prectl =PC_KEP;
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pc_prectl =PC_KEP;
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iack = riack;
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iack = riack;
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NextState_Sreg0 <= `D2_MUL_DLY;
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NextState_Sreg0 <= `D2_MUL_DLY;
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next_delay_counter_Sreg0 <= 34 - 1;
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next_delay_counter_Sreg0 <= 34 - 1;
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zz_is_nop =0;
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zz_is_nop =0;
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end
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end
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`CUR:
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`CUR:
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begin
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begin
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id2ra_ins_clr=ZERO;
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id2ra_ins_clr=ZERO;
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id2ra_ins_cls=ONE;
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id2ra_ins_cls=ONE;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_cls=ONE;
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id2ra_ctl_cls=ONE;
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ra2exec_ctl_clr=ONE;
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ra2exec_ctl_clr=ONE;
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pc_prectl =PC_KEP;
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pc_prectl =PC_KEP;
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iack = riack;
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iack = riack;
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NextState_Sreg0 <= `NOI;
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NextState_Sreg0 <= `NOI;
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zz_is_nop = 1;
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zz_is_nop = 1;
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end
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end
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`RET:
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`RET:
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begin
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begin
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id2ra_ins_clr=ZERO;
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id2ra_ins_clr=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr =ZERO;
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ra2exec_ctl_clr =ZERO;
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pc_prectl =PC_IGN;
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pc_prectl =PC_IGN;
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iack =ZERO;
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iack =ZERO;
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riack =ZERO;
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riack =ZERO;
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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zz_is_nop = ZERO;
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zz_is_nop = ZERO;
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end
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end
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`IRQ:
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`IRQ:
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begin
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begin
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id2ra_ins_clr=ONE;
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id2ra_ins_clr=ONE;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr=ONE;
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ra2exec_ctl_clr=ONE;
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pc_prectl =PC_IRQ;
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pc_prectl =PC_IRQ;
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iack =ONE;
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iack =ONE;
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riack=ONE;
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riack=ONE;
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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zz_is_nop = ZERO;
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zz_is_nop = ZERO;
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end
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end
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`RST:
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`RST:
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begin
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begin
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id2ra_ins_clr=ONE;
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id2ra_ins_clr=ONE;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr=ONE;
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ra2exec_ctl_clr=ONE;
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pc_prectl=PC_RST;
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pc_prectl=PC_RST;
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iack=ZERO;
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iack=ZERO;
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riack=ZERO;
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riack=ZERO;
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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zz_is_nop = ONE;
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zz_is_nop = ONE;
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end
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end
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`LD:
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`LD:
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begin
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begin
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id2ra_ins_clr=ONE;
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id2ra_ins_clr=ONE;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr=ZERO;
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ra2exec_ctl_clr=ZERO;
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pc_prectl =PC_KEP;
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pc_prectl =PC_KEP;
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iack=riack;
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iack=riack;
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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zz_is_nop = ZERO;
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zz_is_nop = ZERO;
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end
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end
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`NOI:
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`NOI:
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begin
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begin
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id2ra_ins_clr=ZERO;
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id2ra_ins_clr=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_clr=ZERO;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr =ZERO;
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ra2exec_ctl_clr =ZERO;
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iack=riack;
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iack=riack;
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pc_prectl=PC_IGN;
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pc_prectl=PC_IGN;
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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zz_is_nop = ZERO;
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zz_is_nop = ZERO;
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end
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end
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`D2_MUL_DLY:
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`D2_MUL_DLY:
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begin
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begin
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id2ra_ins_clr=ONE;
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id2ra_ins_clr=ONE;
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id2ra_ins_cls=ZERO;
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id2ra_ins_cls=ZERO;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_clr=ONE;
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id2ra_ctl_cls=ZERO;
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id2ra_ctl_cls=ZERO;
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ra2exec_ctl_clr=ZERO;
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ra2exec_ctl_clr=ZERO;
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pc_prectl =PC_KEP;
|
pc_prectl =PC_KEP;
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iack=riack;
|
iack=riack;
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zz_is_nop = ONE;
|
zz_is_nop = ONE;
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if (delay_counter_Sreg0 == 0)
|
if (delay_counter_Sreg0 == 0)
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NextState_Sreg0 <= `IDLE;
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NextState_Sreg0 <= `IDLE;
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else
|
else
|
begin
|
begin
|
NextState_Sreg0 <= `D2_MUL_DLY;
|
NextState_Sreg0 <= `D2_MUL_DLY;
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if (delay_counter_Sreg0 != 0) next_delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
|
if (delay_counter_Sreg0 != 0) next_delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
|
end
|
end
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
id2ra_ins_clr=ONE;
|
id2ra_ins_clr=ONE;
|
id2ra_ins_cls=ZERO;
|
id2ra_ins_cls=ZERO;
|
id2ra_ctl_clr=ONE;
|
id2ra_ctl_clr=ONE;
|
id2ra_ctl_cls=ZERO;
|
id2ra_ctl_cls=ZERO;
|
ra2exec_ctl_clr=ONE;
|
ra2exec_ctl_clr=ONE;
|
pc_prectl=PC_RST;
|
pc_prectl=PC_RST;
|
iack=ZERO;
|
iack=ZERO;
|
riack=ZERO;
|
riack=ZERO;
|
zz_is_nop = ONE;
|
zz_is_nop = ONE;
|
NextState_Sreg0 <= `IDLE;
|
NextState_Sreg0 <= `IDLE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
always @ (posedge clk or negedge rst)
|
always @ (posedge clk or negedge rst)
|
begin : Sreg0_CurrentState
|
begin : Sreg0_CurrentState
|
if (~rst)
|
if (~rst)
|
CurrState_Sreg0 <= `RST;
|
CurrState_Sreg0 <= `RST;
|
else
|
else
|
CurrState_Sreg0 <= NextState_Sreg0;
|
CurrState_Sreg0 <= NextState_Sreg0;
|
end
|
end
|
|
|
always @ (posedge clk or negedge rst)
|
always @ (posedge clk or negedge rst)
|
begin : Sreg0_RegOutput
|
begin : Sreg0_RegOutput
|
if (~rst)
|
if (~rst)
|
begin
|
begin
|
delay_counter_Sreg0 <= 0 ; // Initialization in the reset state or default value required!!
|
delay_counter_Sreg0 <= 0 ; // Initialization in the reset state or default value required!!
|
end
|
end
|
else
|
else
|
begin
|
begin
|
delay_counter_Sreg0 <= next_delay_counter_Sreg0;
|
delay_counter_Sreg0 <= next_delay_counter_Sreg0;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
/*
|
/*
|
how to modify this module
|
how to modify this module
|
1,add riack
|
1,add riack
|
2,change the `RST action as default
|
2,change the `RST action as default
|
3,set `IRQ has highest pority.
|
3,set `IRQ has highest pority.
|
*/
|
*/
|
|
|