/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// Author: Liwei ////
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//// Author: Liwei ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// If you encountered any problem, please contact : ////
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//// If you encountered any problem, please contact : ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// ////
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//// ////
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//// Downloaded from: ////
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//// Downloaded from: ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// mcupro@yahoo.com.hk ////
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//// mcupro@yahoo.com.hk ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed freely without ////
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//// This source file may be used and distributed freely without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and any derivative work contains the ////
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//// removed from the file and any derivative work contains the ////
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//// original copyright notice and the associated disclaimer. ////
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//// original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// Please let the author know if it is used ////
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//// Please let the author know if it is used ////
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//// for commercial purpose. ////
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//// for commercial purpose. ////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Date of Creation: 2007.8.1 ////
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//// Date of Creation: 2007.8.1 ////
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//// ////
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//// ////
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//// Version: 0.0.1 ////
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//// Version: 0.0.1 ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// ////
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//// ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Change log: ////
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//// Change log: ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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module exec_stage1
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module exec_stage1
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(
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(
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clk,rst,spc_cls_i,alu_func,
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clk,rst,spc_cls_i,alu_func,
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dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
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dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
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muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
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muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
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muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
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muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
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dmem_data_ur_o,zz_spc_o
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dmem_data_ur_o,zz_spc_o
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);
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);
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input clk;
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input clk;
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wire clk;
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wire clk;
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input rst;
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input rst;
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wire rst;
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wire rst;
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input spc_cls_i;
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input spc_cls_i;
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wire spc_cls_i;
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wire spc_cls_i;
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input [4:0] alu_func;
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input [4:0] alu_func;
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wire [4:0] alu_func;
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wire [4:0] alu_func;
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input [2:0] dmem_fw_ctl;
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input [2:0] dmem_fw_ctl;
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wire [2:0] dmem_fw_ctl;
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wire [2:0] dmem_fw_ctl;
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input [31:0] ext_i;
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input [31:0] ext_i;
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wire [31:0] ext_i;
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wire [31:0] ext_i;
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input [31:0] fw_alu;
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input [31:0] fw_alu;
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wire [31:0] fw_alu;
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wire [31:0] fw_alu;
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input [31:0] fw_dmem;
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input [31:0] fw_dmem;
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wire [31:0] fw_dmem;
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wire [31:0] fw_dmem;
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input [1:0] muxa_ctl_i;
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input [1:0] muxa_ctl_i;
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wire [1:0] muxa_ctl_i;
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wire [1:0] muxa_ctl_i;
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input [2:0] muxa_fw_ctl;
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input [2:0] muxa_fw_ctl;
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wire [2:0] muxa_fw_ctl;
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wire [2:0] muxa_fw_ctl;
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input [1:0] muxb_ctl_i;
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input [1:0] muxb_ctl_i;
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wire [1:0] muxb_ctl_i;
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wire [1:0] muxb_ctl_i;
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input [2:0] muxb_fw_ctl;
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input [2:0] muxb_fw_ctl;
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wire [2:0] muxb_fw_ctl;
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wire [2:0] muxb_fw_ctl;
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input [31:0] pc_i;
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input [31:0] pc_i;
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wire [31:0] pc_i;
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wire [31:0] pc_i;
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input [31:0] rs_i;
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input [31:0] rs_i;
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wire [31:0] rs_i;
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wire [31:0] rs_i;
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input [31:0] rt_i;
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input [31:0] rt_i;
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wire [31:0] rt_i;
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wire [31:0] rt_i;
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output [31:0] alu_ur_o;
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output [31:0] alu_ur_o;
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wire [31:0] alu_ur_o;
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wire [31:0] alu_ur_o;
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output [31:0] dmem_data_ur_o;
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output [31:0] dmem_data_ur_o;
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wire [31:0] dmem_data_ur_o;
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wire [31:0] dmem_data_ur_o;
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output [31:0] zz_spc_o;
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output [31:0] zz_spc_o;
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wire [31:0] zz_spc_o;
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wire [31:0] zz_spc_o;
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wire [31:0] BUS2332;
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wire [31:0] BUS2332;
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wire [31:0] BUS2446;
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wire [31:0] BUS2446;
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wire [31:0] BUS468;
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wire [31:0] BUS468;
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wire [31:0] BUS476;
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wire [31:0] BUS476;
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big_alu MIPS_alu
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big_alu MIPS_alu
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(
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(
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.a(BUS476),
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.a(BUS476),
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.b(BUS468),
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.b(BUS468),
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.c(alu_ur_o),
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.c(alu_ur_o),
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.clk(clk),
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.clk(clk),
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.ctl(alu_func),
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.ctl(alu_func),
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.rst(rst)
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.rst(rst)
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);
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);
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add32 add4
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add32 add4
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(
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(
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.d_i(pc_i),
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.d_i(pc_i),
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.d_o(BUS2446)
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.d_o(BUS2446)
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);
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);
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dmem_data_mux dmem_data_mux
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dmem_data_mux dmem_data_mux
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(
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(
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.data_o(dmem_data_ur_o),
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.data_o(dmem_data_ur_o),
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.fw_alu(fw_alu),
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.fw_alu(fw_alu),
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.fw_ctl(dmem_fw_ctl),
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.fw_ctl(dmem_fw_ctl),
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.fw_dmem(fw_dmem),
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.fw_dmem(fw_dmem),
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.rt(rt_i)
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.rt(rt_i)
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);
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);
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alu_muxa i_alu_muxa
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alu_muxa i_alu_muxa
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(
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(
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.a_o(BUS476),
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.a_o(BUS476),
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.ctl(muxa_ctl_i),
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.ctl(muxa_ctl_i),
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.ext(ext_i),
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.ext(ext_i),
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.fw_alu(fw_alu),
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.fw_alu(fw_alu),
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.fw_ctl(muxa_fw_ctl),
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.fw_ctl(muxa_fw_ctl),
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.fw_mem(fw_dmem),
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.fw_mem(fw_dmem),
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.pc(BUS2332),
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.pc(BUS2332),
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.rs(rs_i),
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.rs(rs_i),
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.spc(zz_spc_o)
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.spc(zz_spc_o)
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);
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);
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alu_muxb i_alu_muxb
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alu_muxb i_alu_muxb
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(
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(
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.b_o(BUS468),
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.b_o(BUS468),
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.ctl(muxb_ctl_i),
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.ctl(muxb_ctl_i),
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.ext(ext_i),
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.ext(ext_i),
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.fw_alu(fw_alu),
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.fw_alu(fw_alu),
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.fw_ctl(muxb_fw_ctl),
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.fw_ctl(muxb_fw_ctl),
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.fw_mem(fw_dmem),
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.fw_mem(fw_dmem),
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.rt(rt_i)
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.rt(rt_i)
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);
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);
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r32_reg pc_nxt
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r32_reg pc_nxt
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(
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(
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.clk(clk),
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.clk(clk),
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.r32_i(BUS2446),
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.r32_i(BUS2446),
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.r32_o(BUS2332)
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.r32_o(BUS2332)
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);
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);
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r32_reg_cls spc
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r32_reg_cls spc
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(
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(
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.clk(clk),
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.clk(clk),
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.cls(spc_cls_i),
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.cls(spc_cls_i),
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.r32_i(pc_i),
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.r32_i(pc_i),
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.r32_o(zz_spc_o)
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.r32_o(zz_spc_o)
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);
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);
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endmodule
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endmodule
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