/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// Author: Liwei ////
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//// Author: Liwei ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// If you encountered any problem, please contact : ////
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//// If you encountered any problem, please contact : ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// ////
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//// ////
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//// Downloaded from: ////
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//// Downloaded from: ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// mcupro@yahoo.com.hk ////
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//// mcupro@yahoo.com.hk ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed freely without ////
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//// This source file may be used and distributed freely without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and any derivative work contains the ////
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//// removed from the file and any derivative work contains the ////
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//// original copyright notice and the associated disclaimer. ////
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//// original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// Please let the author know if it is used ////
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//// Please let the author know if it is used ////
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//// for commercial purpose. ////
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//// for commercial purpose. ////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Date of Creation: 2007.8.1 ////
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//// Date of Creation: 2007.8.1 ////
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//// ////
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//// ////
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//// Version: 0.0.1 ////
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//// Version: 0.0.1 ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// ////
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//// ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Change log: ////
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//// Change log: ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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module rf_stage8 (
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module rf_stage8 (
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clk,irq_i,rst_i,wb_we_i,cmp_ctl_i,
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clk,irq_i,rst_i,wb_we_i,cmp_ctl_i,
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ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt,
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ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt,
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fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl,
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fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl,
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pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o,
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pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o,
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id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o,
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id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o,
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pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o
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pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o
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) ;
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) ;
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// ------------ Port declarations --------- //
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// ------------ Port declarations --------- //
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input clk;
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input clk;
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wire clk;
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wire clk;
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input irq_i;
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input irq_i;
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wire irq_i;
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wire irq_i;
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input rst_i;
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input rst_i;
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wire rst_i;
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wire rst_i;
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input wb_we_i;
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input wb_we_i;
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wire wb_we_i;
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wire wb_we_i;
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input [2:0] cmp_ctl_i;
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input [2:0] cmp_ctl_i;
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wire [2:0] cmp_ctl_i;
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wire [2:0] cmp_ctl_i;
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input [2:0] ext_ctl_i;
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input [2:0] ext_ctl_i;
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wire [2:0] ext_ctl_i;
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wire [2:0] ext_ctl_i;
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input [31:0] fw_alu_i;
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input [31:0] fw_alu_i;
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wire [31:0] fw_alu_i;
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wire [31:0] fw_alu_i;
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input [2:0] fw_cmp_rs;
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input [2:0] fw_cmp_rs;
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wire [2:0] fw_cmp_rs;
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wire [2:0] fw_cmp_rs;
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input [2:0] fw_cmp_rt;
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input [2:0] fw_cmp_rt;
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wire [2:0] fw_cmp_rt;
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wire [2:0] fw_cmp_rt;
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input [31:0] fw_mem_i;
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input [31:0] fw_mem_i;
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wire [31:0] fw_mem_i;
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wire [31:0] fw_mem_i;
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input [2:0] id_cmd;
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input [2:0] id_cmd;
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wire [2:0] id_cmd;
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wire [2:0] id_cmd;
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input [31:0] ins_i;
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input [31:0] ins_i;
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wire [31:0] ins_i;
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wire [31:0] ins_i;
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input [31:0] irq_addr_i;
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input [31:0] irq_addr_i;
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wire [31:0] irq_addr_i;
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wire [31:0] irq_addr_i;
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input [2:0] pc_gen_ctl;
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input [2:0] pc_gen_ctl;
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wire [2:0] pc_gen_ctl;
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wire [2:0] pc_gen_ctl;
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input [31:0] pc_i;
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input [31:0] pc_i;
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wire [31:0] pc_i;
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wire [31:0] pc_i;
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input [1:0] rd_sel_i;
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input [1:0] rd_sel_i;
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wire [1:0] rd_sel_i;
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wire [1:0] rd_sel_i;
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input [4:0] wb_addr_i;
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input [4:0] wb_addr_i;
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wire [4:0] wb_addr_i;
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wire [4:0] wb_addr_i;
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input [31:0] wb_din_i;
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input [31:0] wb_din_i;
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wire [31:0] wb_din_i;
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wire [31:0] wb_din_i;
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input [31:0] zz_spc_i;
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input [31:0] zz_spc_i;
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wire [31:0] zz_spc_i;
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wire [31:0] zz_spc_i;
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output iack_o;
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output iack_o;
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wire iack_o;
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wire iack_o;
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output id2ra_ctl_clr_o;
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output id2ra_ctl_clr_o;
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wire id2ra_ctl_clr_o;
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wire id2ra_ctl_clr_o;
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output id2ra_ctl_cls_o;
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output id2ra_ctl_cls_o;
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wire id2ra_ctl_cls_o;
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wire id2ra_ctl_cls_o;
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output ra2ex_ctl_clr_o;
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output ra2ex_ctl_clr_o;
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wire ra2ex_ctl_clr_o;
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wire ra2ex_ctl_clr_o;
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output [31:0] ext_o;
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output [31:0] ext_o;
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wire [31:0] ext_o;
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wire [31:0] ext_o;
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output [31:0] pc_next;
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output [31:0] pc_next;
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wire [31:0] pc_next;
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wire [31:0] pc_next;
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output [4:0] rd_index_o;
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output [4:0] rd_index_o;
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wire [4:0] rd_index_o;
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wire [4:0] rd_index_o;
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output [4:0] rs_n_o;
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output [4:0] rs_n_o;
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wire [4:0] rs_n_o;
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wire [4:0] rs_n_o;
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output [31:0] rs_o;
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output [31:0] rs_o;
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wire [31:0] rs_o;
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wire [31:0] rs_o;
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output [4:0] rt_n_o;
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output [4:0] rt_n_o;
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wire [4:0] rt_n_o;
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wire [4:0] rt_n_o;
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output [31:0] rt_o;
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output [31:0] rt_o;
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wire [31:0] rt_o;
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wire [31:0] rt_o;
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// ----------------- Constants ------------ //
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// ----------------- Constants ------------ //
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parameter DANGLING_INPUT_CONSTANT = 1'bZ;
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parameter DANGLING_INPUT_CONSTANT = 1'bZ;
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// ----------- Signal declarations -------- //
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// ----------- Signal declarations -------- //
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wire NET6609;
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wire NET6609;
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wire NET6658;
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wire NET6658;
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wire NET7774;
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wire NET7774;
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wire NET904;
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wire NET904;
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wire [3:0] BUS1013;
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wire [3:0] BUS1013;
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wire [31:0] BUS2085;
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wire [31:0] BUS2085;
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wire [4:0] BUS3236;
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wire [4:0] BUS3236;
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wire [4:0] BUS3237;
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wire [4:0] BUS3237;
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wire [4:0] BUS5421;
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wire [4:0] BUS5421;
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wire [31:0] BUS6061;
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wire [31:0] BUS6061;
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wire [31:0] BUS6095;
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wire [31:0] BUS6095;
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// ---- Declaration for Dangling inputs ----//
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// ---- Declaration for Dangling inputs ----//
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wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT;
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wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT;
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// -------- Component instantiations -------//
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// -------- Component instantiations -------//
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cal_cpi CAL_CPI
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cal_cpi CAL_CPI
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(
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(
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.clk(clk),
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.clk(clk),
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.clk_no(CLK_NO),
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.clk_no(CLK_NO),
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.ins_no(INS_NO),
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.ins_no(INS_NO),
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.is_nop(NET7774),
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.is_nop(NET7774),
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.rst(rst_i)
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.rst(rst_i)
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);
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);
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ctl_FSM8 RF_STAGE
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ctl_FSM8 RF_STAGE
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(
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(
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.clk(clk),
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.clk(clk),
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.iack(iack_o),
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.iack(iack_o),
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.id2ra_ctl_clr(id2ra_ctl_clr_o),
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.id2ra_ctl_clr(id2ra_ctl_clr_o),
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.id2ra_ctl_cls(id2ra_ctl_cls_o),
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.id2ra_ctl_cls(id2ra_ctl_cls_o),
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.id2ra_ins_clr(NET6609),
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.id2ra_ins_clr(NET6609),
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.id2ra_ins_cls(NET6658),
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.id2ra_ins_cls(NET6658),
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.id_cmd(id_cmd),
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.id_cmd(id_cmd),
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.irq(irq_i),
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.irq(irq_i),
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.pc_prectl(BUS1013),
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.pc_prectl(BUS1013),
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.ra2exec_ctl_clr(ra2ex_ctl_clr_o),
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.ra2exec_ctl_clr(ra2ex_ctl_clr_o),
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.rst(rst_i),
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.rst(rst_i),
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.zz_is_nop(NET7774)
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.zz_is_nop(NET7774)
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);
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);
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pc_gen2 i_pc_gen
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pc_gen2 i_pc_gen
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(
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(
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.check(NET904),
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.check(NET904),
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.ctl(pc_gen_ctl),
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.ctl(pc_gen_ctl),
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.imm(ext_o),
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.imm(ext_o),
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.irq(irq_addr_i),
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.irq(irq_addr_i),
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.pc(pc_i),
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.pc(pc_i),
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.pc_next(pc_next),
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.pc_next(pc_next),
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.pc_prectl(BUS1013),
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.pc_prectl(BUS1013),
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.s(rs_o),
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.s(rs_o),
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.zz_spc(zz_spc_i)
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.zz_spc(zz_spc_i)
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);
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);
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compare i_cmp
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compare i_cmp
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(
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(
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.ctl(cmp_ctl_i),
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.ctl(cmp_ctl_i),
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.res(NET904),
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.res(NET904),
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.s(rs_o),
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.s(rs_o),
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.t(rt_o)
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.t(rt_o)
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);
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);
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ext i_ext
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ext i_ext
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(
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(
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.ctl(ext_ctl_i),
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.ctl(ext_ctl_i),
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.ins_i(BUS2085),
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.ins_i(BUS2085),
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.res(ext_o)
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.res(ext_o)
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);
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);
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r32_reg_clr_cls ins_reg
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r32_reg_clr_cls ins_reg
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(
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(
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.clk(clk),
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.clk(clk),
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.clr(NET6609),
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.clr(NET6609),
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.cls(NET6658),
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.cls(NET6658),
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.r32_i(ins_i),
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.r32_i(ins_i),
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.r32_o(BUS2085)
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.r32_o(BUS2085)
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);
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);
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jack jack1
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jack jack1
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(
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(
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.ins_i(BUS2085),
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.ins_i(BUS2085),
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.rd_o(BUS5421),
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.rd_o(BUS5421),
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.rs_o(rs_n_o),
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.rs_o(rs_n_o),
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.rt_o(rt_n_o)
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.rt_o(rt_n_o)
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);
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);
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jack jack2
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jack jack2
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(
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(
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.ins_i(ins_i),
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.ins_i(ins_i),
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.rs_o(BUS3237),
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.rs_o(BUS3237),
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.rt_o(BUS3236)
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.rt_o(BUS3236)
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);
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);
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rd_sel rd_sel
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rd_sel rd_sel
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(
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(
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.ctl(rd_sel_i),
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.ctl(rd_sel_i),
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.rd_i(BUS5421),
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.rd_i(BUS5421),
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.rd_o(rd_index_o),
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.rd_o(rd_index_o),
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.rt_i(rt_n_o)
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.rt_i(rt_n_o)
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);
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);
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reg_array2 reg_bank
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reg_array2 reg_bank
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(
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(
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.clock(clk),
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.clock(clk),
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.data(wb_din_i),
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.data(wb_din_i),
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.qa(BUS6061),
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.qa(BUS6061),
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.qb(BUS6095),
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.qb(BUS6095),
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.rd_clk_cls(NET6658),
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.rd_clk_cls(NET6658),
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.rdaddress_a(BUS3237),
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.rdaddress_a(BUS3237),
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.rdaddress_b(BUS3236),
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.rdaddress_b(BUS3236),
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.wraddress(wb_addr_i),
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.wraddress(wb_addr_i),
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.wren(wb_we_i)
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.wren(wb_we_i)
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);
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);
|
|
|
|
|
|
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fwd_mux rf_fwd_rt
|
fwd_mux rf_fwd_rt
|
(
|
(
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.din(BUS6095),
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.din(BUS6095),
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.dout(rt_o),
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.dout(rt_o),
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.fw_alu(fw_alu_i),
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.fw_alu(fw_alu_i),
|
.fw_ctl(fw_cmp_rt),
|
.fw_ctl(fw_cmp_rt),
|
.fw_dmem(fw_mem_i)
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.fw_dmem(fw_mem_i)
|
);
|
);
|
|
|
|
|
|
|
fwd_mux rs_fwd_rs
|
fwd_mux rs_fwd_rs
|
(
|
(
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.din(BUS6061),
|
.din(BUS6061),
|
.dout(rs_o),
|
.dout(rs_o),
|
.fw_alu(fw_alu_i),
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.fw_alu(fw_alu_i),
|
.fw_ctl(fw_cmp_rs),
|
.fw_ctl(fw_cmp_rs),
|
.fw_dmem(fw_mem_i)
|
.fw_dmem(fw_mem_i)
|
);
|
);
|
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|
|
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endmodule
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endmodule
|
|
|
