/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// Author: Liwei ////
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//// Author: Liwei ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// If you encountered any problem, please contact : ////
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//// If you encountered any problem, please contact : ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// Email: mcupro@yahoo.com.hk or mcupro@opencores.org ////
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//// ////
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//// ////
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//// Downloaded from: ////
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//// Downloaded from: ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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//// http://www.opencores.org/pdownloads.cgi/list/mips789 ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// Copyright (C) 2006-2007 Liwei ////
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//// mcupro@yahoo.com.hk ////
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//// mcupro@yahoo.com.hk ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed freely without ////
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//// This source file may be used and distributed freely without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and any derivative work contains the ////
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//// removed from the file and any derivative work contains the ////
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//// original copyright notice and the associated disclaimer. ////
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//// original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// Please let the author know if it is used ////
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//// Please let the author know if it is used ////
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//// for commercial purpose. ////
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//// for commercial purpose. ////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Date of Creation: 2007.8.1 ////
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//// Date of Creation: 2007.8.1 ////
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//// ////
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//// ////
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//// Version: 0.0.1 ////
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//// Version: 0.0.1 ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// ////
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//// ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Change log: ////
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//// Change log: ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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`define FW_ALU 3'b001
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`define FW_ALU 3'b001
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`define FW_MEM 3'b010
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`define FW_MEM 3'b010
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`define FW_NOP 3'b100
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`define FW_NOP 3'b100
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module fw_latch5(input clk,input[4:0]d,output reg [4:0]q);
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module fw_latch5(input clk,input[4:0]d,output reg [4:0]q);
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always @ (posedge clk) q<=d;
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always @ (posedge clk) q<=d;
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endmodule
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endmodule
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module fw_latch1(input clk,input d,output reg q);
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module fw_latch1(input clk,input d,output reg q);
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always @ (posedge clk) q<=d;
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always @ (posedge clk) q<=d;
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endmodule
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endmodule
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module forward_node (
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module forward_node (
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input [4:0]rn,
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input [4:0]rn,
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input [4:0]alu_wr_rn,
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input [4:0]alu_wr_rn,
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input alu_we,
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input alu_we,
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input [4:0]mem_wr_rn,
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input [4:0]mem_wr_rn,
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input mem_we,
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input mem_we,
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output wire[2:0]mux_fw
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output wire[2:0]mux_fw
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);
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);
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assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU:
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assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU:
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((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM:
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((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM:
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`FW_NOP;
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`FW_NOP;
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endmodule
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endmodule
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module forward2 (alu_we,clk,mem_We,fw_alu_rn,fw_mem_rn,rns_i,rnt_i,alu_rs_fw,alu_rt_fw,cmp_rs_fw,
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module forward2 (alu_we,clk,mem_We,fw_alu_rn,fw_mem_rn,rns_i,rnt_i,alu_rs_fw,alu_rt_fw,cmp_rs_fw,
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cmp_rt_fw,dmem_fw) ;
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cmp_rt_fw,dmem_fw) ;
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input alu_we;
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input alu_we;
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wire alu_we;
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wire alu_we;
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input clk;
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input clk;
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wire clk;
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wire clk;
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input mem_We;
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input mem_We;
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wire mem_We;
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wire mem_We;
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input [4:0] fw_alu_rn;
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input [4:0] fw_alu_rn;
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wire [4:0] fw_alu_rn;
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wire [4:0] fw_alu_rn;
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input [4:0] fw_mem_rn;
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input [4:0] fw_mem_rn;
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wire [4:0] fw_mem_rn;
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wire [4:0] fw_mem_rn;
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input [4:0] rns_i;
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input [4:0] rns_i;
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wire [4:0] rns_i;
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wire [4:0] rns_i;
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input [4:0] rnt_i;
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input [4:0] rnt_i;
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wire [4:0] rnt_i;
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wire [4:0] rnt_i;
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output [2:0] alu_rs_fw;
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output [2:0] alu_rs_fw;
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wire [2:0] alu_rs_fw;
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wire [2:0] alu_rs_fw;
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output [2:0] alu_rt_fw;
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output [2:0] alu_rt_fw;
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wire [2:0] alu_rt_fw;
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wire [2:0] alu_rt_fw;
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output [2:0] cmp_rs_fw;
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output [2:0] cmp_rs_fw;
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wire [2:0] cmp_rs_fw;
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wire [2:0] cmp_rs_fw;
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output [2:0] cmp_rt_fw;
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output [2:0] cmp_rt_fw;
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wire [2:0] cmp_rt_fw;
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wire [2:0] cmp_rt_fw;
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output [2:0] dmem_fw;
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output [2:0] dmem_fw;
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wire [2:0] dmem_fw;
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wire [2:0] dmem_fw;
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wire [2:0] BUS1345;
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wire [2:0] BUS1345;
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wire [4:0] BUS82;
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wire [4:0] BUS82;
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wire [4:0] BUS937;
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wire [4:0] BUS937;
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forward_node fw_alu_rs
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forward_node fw_alu_rs
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(
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(
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.alu_we(alu_we),
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.alu_we(alu_we),
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.alu_wr_rn(fw_alu_rn),
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.alu_wr_rn(fw_alu_rn),
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.mem_we(mem_We),
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.mem_we(mem_We),
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.mem_wr_rn(fw_mem_rn),
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.mem_wr_rn(fw_mem_rn),
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.mux_fw(alu_rs_fw),
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.mux_fw(alu_rs_fw),
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.rn(BUS82)
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.rn(BUS82)
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);
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);
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forward_node fw_alu_rt
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forward_node fw_alu_rt
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(
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(
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.alu_we(alu_we),
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.alu_we(alu_we),
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.alu_wr_rn(fw_alu_rn),
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.alu_wr_rn(fw_alu_rn),
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.mem_we(mem_We),
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.mem_we(mem_We),
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.mem_wr_rn(fw_mem_rn),
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.mem_wr_rn(fw_mem_rn),
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.mux_fw(BUS1345),
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.mux_fw(BUS1345),
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.rn(BUS937)
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.rn(BUS937)
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);
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);
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forward_node fw_cmp_rs
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forward_node fw_cmp_rs
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(
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(
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.alu_we(alu_we),
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.alu_we(alu_we),
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.alu_wr_rn(fw_alu_rn),
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.alu_wr_rn(fw_alu_rn),
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.mem_we(mem_We),
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.mem_we(mem_We),
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.mem_wr_rn(fw_mem_rn),
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.mem_wr_rn(fw_mem_rn),
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.mux_fw(cmp_rs_fw),
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.mux_fw(cmp_rs_fw),
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.rn(rns_i)
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.rn(rns_i)
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);
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);
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forward_node fw_cmp_rt
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forward_node fw_cmp_rt
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(
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(
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.alu_we(alu_we),
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.alu_we(alu_we),
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.alu_wr_rn(fw_alu_rn),
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.alu_wr_rn(fw_alu_rn),
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.mem_we(mem_We),
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.mem_we(mem_We),
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.mem_wr_rn(fw_mem_rn),
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.mem_wr_rn(fw_mem_rn),
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.mux_fw(cmp_rt_fw),
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.mux_fw(cmp_rt_fw),
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.rn(rnt_i)
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.rn(rnt_i)
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);
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);
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fw_latch5 fw_reg_rns
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fw_latch5 fw_reg_rns
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(
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(
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.clk(clk),
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.clk(clk),
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.d(rns_i),
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.d(rns_i),
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.q(BUS82)
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.q(BUS82)
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);
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);
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fw_latch5 fw_reg_rnt
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fw_latch5 fw_reg_rnt
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(
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(
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.clk(clk),
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.clk(clk),
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.d(rnt_i),
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.d(rnt_i),
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.q(BUS937)
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.q(BUS937)
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);
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);
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assign alu_rt_fw[2:0] = BUS1345[2:0];
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assign alu_rt_fw[2:0] = BUS1345[2:0];
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assign dmem_fw[2:0] = BUS1345[2:0];
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assign dmem_fw[2:0] = BUS1345[2:0];
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endmodule
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endmodule
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