/******************************************************************
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/******************************************************************
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* *
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* *
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* Author: Liwei *
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* Author: Liwei *
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* *
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* *
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* This file is part of the "mips789" project. *
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* This file is part of the "mips789" project. *
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* Downloaded from: *
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* Downloaded from: *
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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* *
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* *
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* If you encountered any problem, please contact me via *
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* If you encountered any problem, please contact me via *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* *
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* *
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******************************************************************/
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******************************************************************/
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`include "mips789_defs.v"
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`include "mips789_defs.v"
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module exec_stage
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module exec_stage
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(
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(
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clk,rst,spc_cls_i,alu_func,
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clk,rst,spc_cls_i,alu_func,
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dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
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dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
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muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
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muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
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muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
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muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
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dmem_data_ur_o,zz_spc_o
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dmem_data_ur_o,zz_spc_o
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);
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);
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input clk;
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input clk;
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wire clk;
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wire clk;
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input rst;
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input rst;
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wire rst;
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wire rst;
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input spc_cls_i;
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input spc_cls_i;
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wire spc_cls_i;
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wire spc_cls_i;
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input [4:0] alu_func;
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input [4:0] alu_func;
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wire [4:0] alu_func;
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wire [4:0] alu_func;
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input [2:0] dmem_fw_ctl;
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input [2:0] dmem_fw_ctl;
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wire [2:0] dmem_fw_ctl;
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wire [2:0] dmem_fw_ctl;
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input [31:0] ext_i;
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input [31:0] ext_i;
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wire [31:0] ext_i;
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wire [31:0] ext_i;
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input [31:0] fw_alu;
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input [31:0] fw_alu;
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wire [31:0] fw_alu;
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wire [31:0] fw_alu;
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input [31:0] fw_dmem;
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input [31:0] fw_dmem;
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wire [31:0] fw_dmem;
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wire [31:0] fw_dmem;
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input [1:0] muxa_ctl_i;
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input [1:0] muxa_ctl_i;
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wire [1:0] muxa_ctl_i;
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wire [1:0] muxa_ctl_i;
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input [2:0] muxa_fw_ctl;
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input [2:0] muxa_fw_ctl;
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wire [2:0] muxa_fw_ctl;
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wire [2:0] muxa_fw_ctl;
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input [1:0] muxb_ctl_i;
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input [1:0] muxb_ctl_i;
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wire [1:0] muxb_ctl_i;
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wire [1:0] muxb_ctl_i;
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input [2:0] muxb_fw_ctl;
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input [2:0] muxb_fw_ctl;
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wire [2:0] muxb_fw_ctl;
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wire [2:0] muxb_fw_ctl;
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input [31:0] pc_i;
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input [31:0] pc_i;
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wire [31:0] pc_i;
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wire [31:0] pc_i;
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input [31:0] rs_i;
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input [31:0] rs_i;
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wire [31:0] rs_i;
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wire [31:0] rs_i;
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input [31:0] rt_i;
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input [31:0] rt_i;
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wire [31:0] rt_i;
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wire [31:0] rt_i;
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output [31:0] alu_ur_o;
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output [31:0] alu_ur_o;
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wire [31:0] alu_ur_o;
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wire [31:0] alu_ur_o;
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output [31:0] dmem_data_ur_o;
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output [31:0] dmem_data_ur_o;
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wire [31:0] dmem_data_ur_o;
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wire [31:0] dmem_data_ur_o;
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output [31:0] zz_spc_o;
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output [31:0] zz_spc_o;
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wire [31:0] zz_spc_o;
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wire [31:0] zz_spc_o;
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wire [31:0] BUS2332;
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wire [31:0] BUS2332;
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wire [31:0] BUS2446;
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wire [31:0] BUS2446;
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wire [31:0] BUS468;
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wire [31:0] BUS468;
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wire [31:0] BUS476;
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wire [31:0] BUS476;
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big_alu MIPS_alu
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big_alu MIPS_alu
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(
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(
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.a(BUS476),
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.a(BUS476),
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.b(BUS468),
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.b(BUS468),
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.c(alu_ur_o),
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.c(alu_ur_o),
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.clk(clk),
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.clk(clk),
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.ctl(alu_func),
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.ctl(alu_func),
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.rst(rst)
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.rst(rst)
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);
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);
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add32 add4
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add32 add4
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(
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(
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.d_i(pc_i),
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.d_i(pc_i),
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.d_o(BUS2446)
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.d_o(BUS2446)
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);
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);
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fwd_mux dmem_fw_mux
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fwd_mux dmem_fw_mux
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(
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(
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.dout(dmem_data_ur_o),
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.dout(dmem_data_ur_o),
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.fw_alu(fw_alu),
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.fw_alu(fw_alu),
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.fw_ctl(dmem_fw_ctl),
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.fw_ctl(dmem_fw_ctl),
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.fw_dmem(fw_dmem),
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.fw_dmem(fw_dmem),
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.din(rt_i)
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.din(rt_i)
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);
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);
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alu_muxa i_alu_muxa
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alu_muxa i_alu_muxa
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(
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(
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.a_o(BUS476),
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.a_o(BUS476),
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.ctl(muxa_ctl_i),
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.ctl(muxa_ctl_i),
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.ext(ext_i),
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.ext(ext_i),
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.fw_alu(fw_alu),
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.fw_alu(fw_alu),
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.fw_ctl(muxa_fw_ctl),
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.fw_ctl(muxa_fw_ctl),
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.fw_mem(fw_dmem),
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.fw_mem(fw_dmem),
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.pc(BUS2332),
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.pc(BUS2332),
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.rs(rs_i),
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.rs(rs_i),
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.spc(zz_spc_o)
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.spc(zz_spc_o)
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);
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);
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alu_muxb i_alu_muxb
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alu_muxb i_alu_muxb
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(
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(
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.b_o(BUS468),
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.b_o(BUS468),
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.ctl(muxb_ctl_i),
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.ctl(muxb_ctl_i),
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.ext(ext_i),
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.ext(ext_i),
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.fw_alu(fw_alu),
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.fw_alu(fw_alu),
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.fw_ctl(muxb_fw_ctl),
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.fw_ctl(muxb_fw_ctl),
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.fw_mem(fw_dmem),
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.fw_mem(fw_dmem),
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.rt(rt_i)
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.rt(rt_i)
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);
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);
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r32_reg pc_nxt
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r32_reg pc_nxt
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(
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(
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.clk(clk),
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.clk(clk),
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.r32_i(BUS2446),
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.r32_i(BUS2446),
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.r32_o(BUS2332)
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.r32_o(BUS2332)
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);
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);
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r32_reg_cls spc
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r32_reg_cls spc
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(
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(
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.clk(clk),
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.clk(clk),
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.cls(spc_cls_i),
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.cls(spc_cls_i),
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.r32_i(pc_i),
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.r32_i(pc_i),
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.r32_o(zz_spc_o)
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.r32_o(zz_spc_o)
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);
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);
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endmodule
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endmodule
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module big_alu(clk,rst,a,b,c,ctl);
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module big_alu(clk,rst,a,b,c,ctl);
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input clk,rst ;
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input clk,rst ;
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input [31:0] a,b ;
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input [31:0] a,b ;
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output [31:0] c ;
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output [31:0] c ;
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input [4:0]ctl ;
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input [4:0]ctl ;
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wire [31:0] mul_div_c;
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wire [31:0] mul_div_c;
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wire [31:0] alu_c;
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wire [31:0] alu_c;
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wire [31:0] shift_c;
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wire [31:0] shift_c;
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assign c =mul_div_c | alu_c | shift_c ;//save the pc to register
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assign c =mul_div_c | alu_c | shift_c ;//save the pc to register
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muldiv_ff muldiv_ff(
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muldiv_ff muldiv_ff(
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.clk_i(clk),
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.clk_i(clk),
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.rst_i(rst),//sys signal
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.rst_i(rst),//sys signal
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.op_type(ctl),
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.op_type(ctl),
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.op1(a),
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.op1(a),
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.op2(b),
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.op2(b),
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// .busy_o(busy),
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// .busy_o(busy),
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.res(mul_div_c)
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.res(mul_div_c)
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);
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);
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/*
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/*
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muldiv mips_muldiv(
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muldiv mips_muldiv(
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.ready(busy),
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.ready(busy),
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.rst(rst),
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.rst(rst),
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.op1(a),
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.op1(a),
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.op2(b),
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.op2(b),
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.clk(clk),
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.clk(clk),
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.dout(mul_div_c),
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.dout(mul_div_c),
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.func(ctl)
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.func(ctl)
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);
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);
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*/
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*/
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alu mips_alu(
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alu mips_alu(
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.a(a),
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.a(a),
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.b(b),
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.b(b),
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.alu_out(alu_c),
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.alu_out(alu_c),
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.alu_func(ctl)
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.alu_func(ctl)
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|
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);
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);
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shifter_tak mips_shifter(
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shifter_tak mips_shifter(
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.a(b),
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.a(b),
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.shift_out(shift_c),
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.shift_out(shift_c),
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.shift_func(ctl),
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.shift_func(ctl),
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.shift_amount(a)
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.shift_amount(a)
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);
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);
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endmodule
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endmodule
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module alu_muxa(
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module alu_muxa(
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input [31:0]spc,
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input [31:0]spc,
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input [31:0]pc,
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input [31:0]pc,
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input [31:0]fw_mem,
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input [31:0]fw_mem,
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input [31:0]rs,
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input [31:0]rs,
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input [31:0]fw_alu,
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input [31:0]fw_alu,
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input [31:0]ext,
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input [31:0]ext,
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input [1:0] ctl,
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input [1:0] ctl,
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input [2:0] fw_ctl,
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input [2:0] fw_ctl,
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output reg [31:0]a_o
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output reg [31:0]a_o
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);
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);
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always @(*)
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always @(*)
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begin
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begin
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case (ctl)
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case (ctl)
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`MUXA_RS: a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs;
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`MUXA_RS: a_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rs;
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`MUXA_PC: a_o = pc;
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`MUXA_PC: a_o = pc;
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`MUXA_EXT: a_o = ext;
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`MUXA_EXT: a_o = ext;
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`MUXA_SPC: a_o = spc;
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`MUXA_SPC: a_o = spc;
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default : a_o = rs;
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default : a_o = rs;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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module alu_muxb(
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module alu_muxb(
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input [31:0] rt,
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input [31:0] rt,
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input [31:0]fw_alu,
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input [31:0]fw_alu,
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input [31:0]fw_mem,
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input [31:0]fw_mem,
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input [31:0]ext ,
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input [31:0]ext ,
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input [1:0]ctl ,
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input [1:0]ctl ,
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input [2:0]fw_ctl ,
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input [2:0]fw_ctl ,
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output reg [31:0] b_o
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output reg [31:0] b_o
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);
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);
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always@(*)
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always@(*)
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case (ctl)
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case (ctl)
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`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
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`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
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`MUXB_EXT : b_o=ext;
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`MUXB_EXT : b_o=ext;
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default b_o=rt;
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default b_o=rt;
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endcase
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endcase
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endmodule
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endmodule
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//This file is based on YACC ->alu.v and UCORE ->alu.v
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//This file is based on YACC ->alu.v and UCORE ->alu.v
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module alu (a,b,alu_out,alu_func);
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module alu (a,b,alu_out,alu_func);
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|
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input [31:0] a,b;
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input [31:0] a,b;
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output reg [31:0] alu_out;
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output reg [31:0] alu_out;
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input [4:0] alu_func;
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input [4:0] alu_func;
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reg [32:0] sum;
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reg [32:0] sum;
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|
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always @(*)
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always @(*)
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begin
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begin
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case (alu_func)
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case (alu_func)
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|
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`ALU_PA : alu_out=a;
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`ALU_PA : alu_out=a;
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`ALU_PB : alu_out=b;
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`ALU_PB : alu_out=b;
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`ALU_ADD : alu_out=a+b;
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`ALU_ADD : alu_out=a+b;
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`ALU_SUB ,
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`ALU_SUB ,
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`ALU_SUBU : alu_out=a + (~b)+1;
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`ALU_SUBU : alu_out=a + (~b)+1;
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`ALU_OR : alu_out=a | b;
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`ALU_OR : alu_out=a | b;
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`ALU_AND : alu_out=a & b;
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`ALU_AND : alu_out=a & b;
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`ALU_XOR : alu_out=a ^ b;
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`ALU_XOR : alu_out=a ^ b;
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`ALU_NOR : alu_out=~(a | b);
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`ALU_NOR : alu_out=~(a | b);
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`ALU_SLTU : alu_out=(a < b)?1:0;
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`ALU_SLTU : alu_out=(a < b)?1:0;
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`ALU_SLT :
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`ALU_SLT :
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begin
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begin
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sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;
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sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;
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alu_out={31'h0000_0000,sum[32]};
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alu_out={31'h0000_0000,sum[32]};
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end
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end
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default : alu_out=32'h0;
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default : alu_out=32'h0;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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|
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module
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module
|
shifter_tak(
|
shifter_tak(
|
input [31:0] a,
|
input [31:0] a,
|
output reg [31:0] shift_out,
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output reg [31:0] shift_out,
|
input [4:0] shift_func,//connect to alu_func_ctl
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input [4:0] shift_func,//connect to alu_func_ctl
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input [31:0] shift_amount//connect to b
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input [31:0] shift_amount//connect to b
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);
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);
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|
|
always @ (*)
|
always @ (*)
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begin
|
begin
|
if( shift_func == `ALU_SLL )
|
if( shift_func == `ALU_SLL )
|
begin
|
begin
|
case ( shift_amount[4:0] )
|
case ( shift_amount[4:0] )
|
5'b00000: shift_out=a;
|
5'b00000: shift_out=a;
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5'b00001: shift_out={a[30:0],1'b0};
|
5'b00001: shift_out={a[30:0],1'b0};
|
5'b00010: shift_out={a[29:0],2'b0};
|
5'b00010: shift_out={a[29:0],2'b0};
|
5'b00011: shift_out={a[28:0],3'b0};
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5'b00011: shift_out={a[28:0],3'b0};
|
5'b00100: shift_out={a[27:0],4'b0};
|
5'b00100: shift_out={a[27:0],4'b0};
|
5'b00101: shift_out={a[26:0],5'b0};
|
5'b00101: shift_out={a[26:0],5'b0};
|
5'b00110: shift_out={a[25:0],6'b0};
|
5'b00110: shift_out={a[25:0],6'b0};
|
5'b00111: shift_out={a[24:0],7'b0};
|
5'b00111: shift_out={a[24:0],7'b0};
|
5'b01000: shift_out={a[23:0],8'b0};
|
5'b01000: shift_out={a[23:0],8'b0};
|
5'b01001: shift_out={a[22:0],9'b0};
|
5'b01001: shift_out={a[22:0],9'b0};
|
5'b01010: shift_out={a[21:0],10'b0};
|
5'b01010: shift_out={a[21:0],10'b0};
|
5'b01011: shift_out={a[20:0],11'b0};
|
5'b01011: shift_out={a[20:0],11'b0};
|
5'b01100: shift_out={a[19:0],12'b0};
|
5'b01100: shift_out={a[19:0],12'b0};
|
5'b01101: shift_out={a[18:0],13'b0};
|
5'b01101: shift_out={a[18:0],13'b0};
|
5'b01110: shift_out={a[17:0],14'b0};
|
5'b01110: shift_out={a[17:0],14'b0};
|
5'b01111: shift_out={a[16:0],15'b0};
|
5'b01111: shift_out={a[16:0],15'b0};
|
5'b10000: shift_out={a[15:0],16'b0};
|
5'b10000: shift_out={a[15:0],16'b0};
|
5'b10001: shift_out={a[14:0],17'b0};
|
5'b10001: shift_out={a[14:0],17'b0};
|
5'b10010: shift_out={a[13:0],18'b0};
|
5'b10010: shift_out={a[13:0],18'b0};
|
5'b10011: shift_out={a[12:0],19'b0};
|
5'b10011: shift_out={a[12:0],19'b0};
|
5'b10100: shift_out={a[11:0],20'b0};
|
5'b10100: shift_out={a[11:0],20'b0};
|
5'b10101: shift_out={a[10:0],21'b0};
|
5'b10101: shift_out={a[10:0],21'b0};
|
5'b10110: shift_out={a[9:0],22'b0};
|
5'b10110: shift_out={a[9:0],22'b0};
|
5'b10111: shift_out={a[8:0],23'b0};
|
5'b10111: shift_out={a[8:0],23'b0};
|
5'b11000: shift_out={a[7:0],24'b0};
|
5'b11000: shift_out={a[7:0],24'b0};
|
5'b11001: shift_out={a[6:0],25'b0};
|
5'b11001: shift_out={a[6:0],25'b0};
|
5'b11010: shift_out={a[5:0],26'b0};
|
5'b11010: shift_out={a[5:0],26'b0};
|
5'b11011: shift_out={a[4:0],27'b0};
|
5'b11011: shift_out={a[4:0],27'b0};
|
5'b11100: shift_out={a[3:0],28'b0};
|
5'b11100: shift_out={a[3:0],28'b0};
|
5'b11101: shift_out={a[2:0],29'b0};
|
5'b11101: shift_out={a[2:0],29'b0};
|
5'b11110: shift_out={a[1:0],30'b0};
|
5'b11110: shift_out={a[1:0],30'b0};
|
5'b11111: shift_out={a[0],31'b0};
|
5'b11111: shift_out={a[0],31'b0};
|
default shift_out ='d0;
|
default shift_out ='d0;
|
endcase
|
endcase
|
end else if (shift_func== `ALU_SRL) begin
|
end else if (shift_func== `ALU_SRL) begin
|
case (shift_amount[4:0])
|
case (shift_amount[4:0])
|
5'b00000: shift_out=a;
|
5'b00000: shift_out=a;
|
5'b00001: shift_out={1'b0,a[31:1]};
|
5'b00001: shift_out={1'b0,a[31:1]};
|
5'b00010: shift_out={2'b0,a[31:2]};
|
5'b00010: shift_out={2'b0,a[31:2]};
|
5'b00011: shift_out={3'b0,a[31:3]};
|
5'b00011: shift_out={3'b0,a[31:3]};
|
5'b00100: shift_out={4'b0,a[31:4]};
|
5'b00100: shift_out={4'b0,a[31:4]};
|
5'b00101: shift_out={5'b0,a[31:5]};
|
5'b00101: shift_out={5'b0,a[31:5]};
|
5'b00110: shift_out={6'b0,a[31:6]};
|
5'b00110: shift_out={6'b0,a[31:6]};
|
5'b00111: shift_out={7'b0,a[31:7]};
|
5'b00111: shift_out={7'b0,a[31:7]};
|
5'b01000: shift_out={8'b0,a[31:8]};
|
5'b01000: shift_out={8'b0,a[31:8]};
|
5'b01001: shift_out={9'b0,a[31:9]};
|
5'b01001: shift_out={9'b0,a[31:9]};
|
5'b01010: shift_out={10'b0,a[31:10]};
|
5'b01010: shift_out={10'b0,a[31:10]};
|
5'b01011: shift_out={11'b0,a[31:11]};
|
5'b01011: shift_out={11'b0,a[31:11]};
|
5'b01100: shift_out={12'b0,a[31:12]};
|
5'b01100: shift_out={12'b0,a[31:12]};
|
5'b01101: shift_out={13'b0,a[31:13]};
|
5'b01101: shift_out={13'b0,a[31:13]};
|
5'b01110: shift_out={14'b0,a[31:14]};
|
5'b01110: shift_out={14'b0,a[31:14]};
|
5'b01111: shift_out={15'b0,a[31:15]};
|
5'b01111: shift_out={15'b0,a[31:15]};
|
5'b10000: shift_out={16'b0,a[31:16]};
|
5'b10000: shift_out={16'b0,a[31:16]};
|
5'b10001: shift_out={17'b0,a[31:17]};
|
5'b10001: shift_out={17'b0,a[31:17]};
|
5'b10010: shift_out={18'b0,a[31:18]};
|
5'b10010: shift_out={18'b0,a[31:18]};
|
5'b10011: shift_out={19'b0,a[31:19]};
|
5'b10011: shift_out={19'b0,a[31:19]};
|
5'b10100: shift_out={20'b0,a[31:20]};
|
5'b10100: shift_out={20'b0,a[31:20]};
|
5'b10101: shift_out={21'b0,a[31:21]};
|
5'b10101: shift_out={21'b0,a[31:21]};
|
5'b10110: shift_out={22'b0,a[31:22]};
|
5'b10110: shift_out={22'b0,a[31:22]};
|
5'b10111: shift_out={23'b0,a[31:23]};
|
5'b10111: shift_out={23'b0,a[31:23]};
|
5'b11000: shift_out={24'b0,a[31:24]};
|
5'b11000: shift_out={24'b0,a[31:24]};
|
5'b11001: shift_out={25'b0,a[31:25]};
|
5'b11001: shift_out={25'b0,a[31:25]};
|
5'b11010: shift_out={26'b0,a[31:26]};
|
5'b11010: shift_out={26'b0,a[31:26]};
|
5'b11011: shift_out={27'b0,a[31:27]};
|
5'b11011: shift_out={27'b0,a[31:27]};
|
5'b11100: shift_out={28'b0,a[31:28]};
|
5'b11100: shift_out={28'b0,a[31:28]};
|
5'b11101: shift_out={29'b0,a[31:29]};
|
5'b11101: shift_out={29'b0,a[31:29]};
|
5'b11110: shift_out={30'b0,a[31:30]};
|
5'b11110: shift_out={30'b0,a[31:30]};
|
5'b11111: shift_out={31'b0,a[31:31]};
|
5'b11111: shift_out={31'b0,a[31:31]};
|
default : shift_out = 0;
|
default : shift_out = 0;
|
endcase
|
endcase
|
end else
|
end else
|
if (shift_func==`ALU_SRA)
|
if (shift_func==`ALU_SRA)
|
begin// SHIFT_RIGHT_SIGNED
|
begin// SHIFT_RIGHT_SIGNED
|
case ( shift_amount[4:0])
|
case ( shift_amount[4:0])
|
5'b00000: shift_out=a;
|
5'b00000: shift_out=a;
|
5'b00001: shift_out={a[31],a[31:1]};
|
5'b00001: shift_out={a[31],a[31:1]};
|
5'b00010: shift_out={{2{a[31]}},a[31:2]};
|
5'b00010: shift_out={{2{a[31]}},a[31:2]};
|
5'b00011: shift_out={{3{a[31]}},a[31:3]};
|
5'b00011: shift_out={{3{a[31]}},a[31:3]};
|
5'b00100: shift_out={{4{a[31]}},a[31:4]};
|
5'b00100: shift_out={{4{a[31]}},a[31:4]};
|
5'b00101: shift_out={{5{a[31]}},a[31:5]};
|
5'b00101: shift_out={{5{a[31]}},a[31:5]};
|
5'b00110: shift_out={{6{a[31]}},a[31:6]};
|
5'b00110: shift_out={{6{a[31]}},a[31:6]};
|
5'b00111: shift_out={{7{a[31]}},a[31:7]};
|
5'b00111: shift_out={{7{a[31]}},a[31:7]};
|
5'b01000: shift_out={{8{a[31]}},a[31:8]};
|
5'b01000: shift_out={{8{a[31]}},a[31:8]};
|
5'b01001: shift_out={{9{a[31]}},a[31:9]};
|
5'b01001: shift_out={{9{a[31]}},a[31:9]};
|
5'b01010: shift_out={{10{a[31]}},a[31:10]};
|
5'b01010: shift_out={{10{a[31]}},a[31:10]};
|
5'b01011: shift_out={{11{a[31]}},a[31:11]};
|
5'b01011: shift_out={{11{a[31]}},a[31:11]};
|
5'b01100: shift_out={{12{a[31]}},a[31:12]};
|
5'b01100: shift_out={{12{a[31]}},a[31:12]};
|
5'b01101: shift_out={{13{a[31]}},a[31:13]};
|
5'b01101: shift_out={{13{a[31]}},a[31:13]};
|
5'b01110: shift_out={{14{a[31]}},a[31:14]};
|
5'b01110: shift_out={{14{a[31]}},a[31:14]};
|
5'b01111: shift_out={{15{a[31]}},a[31:15]};
|
5'b01111: shift_out={{15{a[31]}},a[31:15]};
|
5'b10000: shift_out={{16{a[31]}},a[31:16]};
|
5'b10000: shift_out={{16{a[31]}},a[31:16]};
|
5'b10001: shift_out={{17{a[31]}},a[31:17]};
|
5'b10001: shift_out={{17{a[31]}},a[31:17]};
|
5'b10010: shift_out={{18{a[31]}},a[31:18]};
|
5'b10010: shift_out={{18{a[31]}},a[31:18]};
|
5'b10011: shift_out={{19{a[31]}},a[31:19]};
|
5'b10011: shift_out={{19{a[31]}},a[31:19]};
|
5'b10100: shift_out={{20{a[31]}},a[31:20]};
|
5'b10100: shift_out={{20{a[31]}},a[31:20]};
|
5'b10101: shift_out={{21{a[31]}},a[31:21]};
|
5'b10101: shift_out={{21{a[31]}},a[31:21]};
|
5'b10110: shift_out={{22{a[31]}},a[31:22]};
|
5'b10110: shift_out={{22{a[31]}},a[31:22]};
|
5'b10111: shift_out={{23{a[31]}},a[31:23]};
|
5'b10111: shift_out={{23{a[31]}},a[31:23]};
|
5'b11000: shift_out={{24{a[31]}},a[31:24]};
|
5'b11000: shift_out={{24{a[31]}},a[31:24]};
|
5'b11001: shift_out={{25{a[31]}},a[31:25]};
|
5'b11001: shift_out={{25{a[31]}},a[31:25]};
|
5'b11010: shift_out={{26{a[31]}},a[31:26]};
|
5'b11010: shift_out={{26{a[31]}},a[31:26]};
|
5'b11011: shift_out={{27{a[31]}},a[31:27]};
|
5'b11011: shift_out={{27{a[31]}},a[31:27]};
|
5'b11100: shift_out={{28{a[31]}},a[31:28]};
|
5'b11100: shift_out={{28{a[31]}},a[31:28]};
|
5'b11101: shift_out={{29{a[31]}},a[31:29]};
|
5'b11101: shift_out={{29{a[31]}},a[31:29]};
|
5'b11110: shift_out={{30{a[31]}},a[31:30]};
|
5'b11110: shift_out={{30{a[31]}},a[31:30]};
|
5'b11111: shift_out={{31{a[31]}},a[31:31]};
|
5'b11111: shift_out={{31{a[31]}},a[31:31]};
|
default shift_out='d0;
|
default shift_out='d0;
|
endcase
|
endcase
|
end
|
end
|
else shift_out='d0;
|
else shift_out='d0;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
module muldiv(ready,rst,op1,op2,clk,dout,func);
|
module muldiv(ready,rst,op1,op2,clk,dout,func);
|
input clk,rst;
|
input clk,rst;
|
wire sign;
|
wire sign;
|
input [4:0] func ;
|
input [4:0] func ;
|
input [31:0] op2, op1;
|
input [31:0] op2, op1;
|
output [31:0] dout;
|
output [31:0] dout;
|
output ready;
|
output ready;
|
reg [31:0] quotient, quotient_temp;
|
reg [31:0] quotient, quotient_temp;
|
reg [63:0] dividend_copy, divider_copy, diff;
|
reg [63:0] dividend_copy, divider_copy, diff;
|
reg negative_output;
|
reg negative_output;
|
|
|
reg [63:0] product, product_temp;
|
reg [63:0] product, product_temp;
|
|
|
reg [31:0] multiplier_copy;
|
reg [31:0] multiplier_copy;
|
reg [63:0] multiplicand_copy;
|
reg [63:0] multiplicand_copy;
|
|
|
reg [6:0] mul_bit,div_bit;
|
reg [6:0] mul_bit,div_bit;
|
wire ready = ((mul_bit==0)&&(div_bit==0));
|
wire ready = ((mul_bit==0)&&(div_bit==0));
|
|
|
wire [31:0] dividend, divider;
|
wire [31:0] dividend, divider;
|
|
|
wire [31:0] remainder;
|
wire [31:0] remainder;
|
wire [31:0] multiplier,multiplicand;
|
wire [31:0] multiplier,multiplicand;
|
|
|
reg [31:0] hi,lo;
|
reg [31:0] hi,lo;
|
|
|
assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0;
|
assign dout = (func==`ALU_MFHI)?hi:(func==`ALU_MFLO)?lo:0;
|
|
|
assign remainder = (!negative_output) ?
|
assign remainder = (!negative_output) ?
|
dividend_copy[31:0] :
|
dividend_copy[31:0] :
|
~dividend_copy[31:0] + 1'b1;
|
~dividend_copy[31:0] + 1'b1;
|
|
|
assign multiplier=op2;
|
assign multiplier=op2;
|
assign multiplicand=op1;
|
assign multiplicand=op1;
|
assign dividend=op1;
|
assign dividend=op1;
|
assign divider = op2;
|
assign divider = op2;
|
assign sign = ((func==`ALU_MULT)||(func==`ALU_DIV));
|
assign sign = ((func==`ALU_MULT)||(func==`ALU_DIV));
|
|
|
initial
|
initial
|
begin
|
begin
|
hi=0;
|
hi=0;
|
lo=0;
|
lo=0;
|
end
|
end
|
always @( posedge clk /*or negedge rst */)
|
always @( posedge clk /*or negedge rst */)
|
if (~rst)
|
if (~rst)
|
begin
|
begin
|
mul_bit=0;
|
mul_bit=0;
|
div_bit=0;
|
div_bit=0;
|
/*
|
/*
|
hi=0;
|
hi=0;
|
lo=0;
|
lo=0;
|
*/
|
*/
|
negative_output = 0;
|
negative_output = 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if((ready)&&((func==`ALU_MULT)||(func==`ALU_MULTTU)))
|
if((ready)&&((func==`ALU_MULT)||(func==`ALU_MULTTU)))
|
begin
|
begin
|
mul_bit = 33;
|
mul_bit = 33;
|
product = 0;
|
product = 0;
|
product_temp = 0;
|
product_temp = 0;
|
multiplicand_copy = (!sign || !multiplicand[31]) ?
|
multiplicand_copy = (!sign || !multiplicand[31]) ?
|
{ 32'd0, multiplicand } :
|
{ 32'd0, multiplicand } :
|
{ 32'd0, ~multiplicand + 1'b1};
|
{ 32'd0, ~multiplicand + 1'b1};
|
multiplier_copy = (!sign || !multiplier[31]) ?multiplier :~multiplier + 1'b1;
|
multiplier_copy = (!sign || !multiplier[31]) ?multiplier :~multiplier + 1'b1;
|
|
|
negative_output = sign &&
|
negative_output = sign &&
|
((multiplier[31] && !multiplicand[31])
|
((multiplier[31] && !multiplicand[31])
|
||(!multiplier[31] && multiplicand[31]));
|
||(!multiplier[31] && multiplicand[31]));
|
end
|
end
|
if ( mul_bit > 1 )
|
if ( mul_bit > 1 )
|
begin
|
begin
|
|
|
if( multiplier_copy[0] == 1'b1 )
|
if( multiplier_copy[0] == 1'b1 )
|
product_temp = product_temp +multiplicand_copy;
|
product_temp = product_temp +multiplicand_copy;
|
|
|
|
|
product = (!negative_output) ?
|
product = (!negative_output) ?
|
product_temp :
|
product_temp :
|
~product_temp + 1'b1;
|
~product_temp + 1'b1;
|
|
|
multiplier_copy = multiplier_copy >> 1;
|
multiplier_copy = multiplier_copy >> 1;
|
multiplicand_copy = multiplicand_copy << 1;
|
multiplicand_copy = multiplicand_copy << 1;
|
mul_bit = mul_bit - 1'b1;
|
mul_bit = mul_bit - 1'b1;
|
end
|
end
|
else if (mul_bit == 1)
|
else if (mul_bit == 1)
|
begin
|
begin
|
hi = product[63:32];
|
hi = product[63:32];
|
lo = product[31:0];
|
lo = product[31:0];
|
mul_bit=0;
|
mul_bit=0;
|
end
|
end
|
|
|
if((ready)&&((func==`ALU_DIV)||(func==`ALU_DIVU)))
|
if((ready)&&((func==`ALU_DIV)||(func==`ALU_DIVU)))
|
begin
|
begin
|
div_bit = 33;
|
div_bit = 33;
|
quotient = 0;
|
quotient = 0;
|
quotient_temp = 0;
|
quotient_temp = 0;
|
dividend_copy = (!sign || !dividend[31]) ?
|
dividend_copy = (!sign || !dividend[31]) ?
|
{32'd0,dividend} :
|
{32'd0,dividend} :
|
{32'd0,~dividend + 1'b1};
|
{32'd0,~dividend + 1'b1};
|
|
|
divider_copy = (!sign || !divider[31]) ?
|
divider_copy = (!sign || !divider[31]) ?
|
{1'b0,divider,31'd0} :
|
{1'b0,divider,31'd0} :
|
{1'b0,~divider + 1'b1,31'd0};
|
{1'b0,~divider + 1'b1,31'd0};
|
|
|
negative_output = sign &&
|
negative_output = sign &&
|
((divider[31] && !dividend[31])
|
((divider[31] && !dividend[31])
|
||(!divider[31] && dividend[31]));
|
||(!divider[31] && dividend[31]));
|
end
|
end
|
else if (div_bit > 1)
|
else if (div_bit > 1)
|
begin
|
begin
|
diff = dividend_copy - divider_copy;
|
diff = dividend_copy - divider_copy;
|
quotient_temp = quotient_temp << 1;
|
quotient_temp = quotient_temp << 1;
|
if( !diff[63] )
|
if( !diff[63] )
|
begin
|
begin
|
dividend_copy = diff;
|
dividend_copy = diff;
|
quotient_temp[0] = 1'd1;
|
quotient_temp[0] = 1'd1;
|
end
|
end
|
quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1;
|
quotient = (!negative_output) ?quotient_temp :~quotient_temp + 1'b1;
|
divider_copy = divider_copy >> 1;
|
divider_copy = divider_copy >> 1;
|
div_bit = div_bit - 1'b1;
|
div_bit = div_bit - 1'b1;
|
end
|
end
|
else if (div_bit == 1)
|
else if (div_bit == 1)
|
begin
|
begin
|
lo = quotient;
|
lo = quotient;
|
hi = remainder;
|
hi = remainder;
|
div_bit=0;
|
div_bit=0;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
//creatied by Zhangfeifei
|
//creatied by Zhangfeifei
|
//modified by Liwei
|
//modified by Liwei
|
module muldiv_ff
|
module muldiv_ff
|
(
|
(
|
clk_i,rst_i,
|
clk_i,rst_i,
|
op_type,op1,op2,
|
op_type,op1,op2,
|
rdy,res
|
rdy,res
|
);
|
);
|
|
|
parameter OP_MULT = `ALU_MULT;
|
parameter OP_MULT = `ALU_MULT;
|
parameter OP_MULTU = `ALU_MULTU;
|
parameter OP_MULTU = `ALU_MULTU;
|
parameter OP_DIV = `ALU_DIV;
|
parameter OP_DIV = `ALU_DIV;
|
parameter OP_DIVU = `ALU_DIVU;
|
parameter OP_DIVU = `ALU_DIVU;
|
parameter OP_MFHI = `ALU_MFHI;
|
parameter OP_MFHI = `ALU_MFHI;
|
parameter OP_MFLO = `ALU_MFLO;
|
parameter OP_MFLO = `ALU_MFLO;
|
|
|
parameter OP_MTHI = `ALU_MTHI;
|
parameter OP_MTHI = `ALU_MTHI;
|
parameter OP_MTLO = `ALU_MTLO;
|
parameter OP_MTLO = `ALU_MTLO;
|
|
|
parameter OP_NONE = `ALU_NOP;
|
parameter OP_NONE = `ALU_NOP;
|
|
|
input clk_i;
|
input clk_i;
|
input rst_i;
|
input rst_i;
|
input [4:0] op_type;
|
input [4:0] op_type;
|
input [31:0] op1;
|
input [31:0] op1;
|
input [31:0] op2;
|
input [31:0] op2;
|
output [31:0] res;
|
output [31:0] res;
|
output rdy;
|
output rdy;
|
|
|
reg rdy;
|
reg rdy;
|
|
|
reg [64:0] hilo;
|
reg [64:0] hilo;
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reg [32:0] op2_reged;
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reg [32:0] op2_reged;
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reg [5:0] count;
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reg [5:0] count;
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reg op1_sign_reged;
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reg op1_sign_reged;
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reg op2_sign_reged;
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reg op2_sign_reged;
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reg sub_or_yn;
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reg sub_or_yn;
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|
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wire [32:0] nop2_reged;
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wire [32:0] nop2_reged;
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assign nop2_reged = ~op2_reged +1;
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assign nop2_reged = ~op2_reged +1;
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|
|
reg sign;
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reg sign;
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reg mul;
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reg mul;
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reg start;
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reg start;
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|
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assign res = (op_type == OP_MFLO )?hilo[31:0]:((op_type == OP_MFHI))?hilo[63:32]:0;//op_type == OP_MFHI or other
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assign res = (op_type == OP_MFLO )?hilo[31:0]:((op_type == OP_MFHI))?hilo[63:32]:0;//op_type == OP_MFHI or other
|
|
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reg overflow;
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reg overflow;
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reg finish;
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reg finish;
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reg add1; //if the quotient will add 1 at the end of the divide operation
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reg add1; //if the quotient will add 1 at the end of the divide operation
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reg addop2; //if the remainder will add op2 at the end of the divide operation
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reg addop2; //if the remainder will add op2 at the end of the divide operation
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reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation
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reg addnop2;//if the remainder will add ~op2+1 at the end of the divide operation
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|
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|
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always @( posedge clk_i /*or negedge rst_i*/)
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always @( posedge clk_i /*or negedge rst_i*/)
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begin
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begin
|
if(~rst_i)
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if(~rst_i)
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begin
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begin
|
count = 6'bx;
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count = 6'bx;
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hilo = 65'b0;
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hilo = 65'b0;
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op2_reged = 33'bx;
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op2_reged = 33'bx;
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op1_sign_reged = 1'bx;
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op1_sign_reged = 1'bx;
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op2_sign_reged = 1'bx;
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op2_sign_reged = 1'bx;
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sub_or_yn = 1'bx;
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sub_or_yn = 1'bx;
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rdy = 1'b1;
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rdy = 1'b1;
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start = 1'bx;
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start = 1'bx;
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sign = 1'bx;
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sign = 1'bx;
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mul = 1'bx;
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mul = 1'bx;
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|
|
finish = 1'bx;
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finish = 1'bx;
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add1 = 1'bx;
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add1 = 1'bx;
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addop2 = 1'bx;
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addop2 = 1'bx;
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addnop2 = 1'bx;
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addnop2 = 1'bx;
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end
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end
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else begin
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else begin
|
|
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if(op_type == OP_MTHI || op_type == OP_MTLO)
|
if(op_type == OP_MTHI || op_type == OP_MTLO)
|
begin
|
begin
|
if(op_type == OP_MTHI) hilo[64:32] = {1'b0,op1};
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if(op_type == OP_MTHI) hilo[64:32] = {1'b0,op1};
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if(op_type == OP_MTLO) hilo[31:0] = op1;
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if(op_type == OP_MTLO) hilo[31:0] = op1;
|
rdy = 1;
|
rdy = 1;
|
end
|
end
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else if(rdy)
|
else if(rdy)
|
begin
|
begin
|
start = (op_type == OP_MULT) || (op_type == OP_MULTU) || (op_type == OP_DIV) || (op_type == OP_DIVU);
|
start = (op_type == OP_MULT) || (op_type == OP_MULTU) || (op_type == OP_DIV) || (op_type == OP_DIVU);
|
mul = (op_type == OP_MULT) || (op_type == OP_MULTU);
|
mul = (op_type == OP_MULT) || (op_type == OP_MULTU);
|
sign = (op_type == OP_MULT) || (op_type == OP_DIV);
|
sign = (op_type == OP_MULT) || (op_type == OP_DIV);
|
|
|
if(start)
|
if(start)
|
begin:START_SECTION
|
begin:START_SECTION
|
reg [32:0] over;
|
reg [32:0] over;
|
|
|
op2_reged = {sign ?op2[31] :1'b0 ,op2};
|
op2_reged = {sign ?op2[31] :1'b0 ,op2};
|
hilo = {~mul && sign?{33{op1[31]}}:33'b0,op1};
|
hilo = {~mul && sign?{33{op1[31]}}:33'b0,op1};
|
count = 6'b000000;
|
count = 6'b000000;
|
rdy = 0;
|
rdy = 0;
|
op1_sign_reged = sign?op1[31]:0;
|
op1_sign_reged = sign?op1[31]:0;
|
op2_sign_reged = sign?op2[31]:0;
|
op2_sign_reged = sign?op2[31]:0;
|
sub_or_yn = 0;
|
sub_or_yn = 0;
|
|
|
over = ~op2_reged + {op1[31],op1};
|
over = ~op2_reged + {op1[31],op1};
|
overflow = sign && ~mul ? op1_sign_reged && op2_sign_reged && ~over[32] : 0;
|
overflow = sign && ~mul ? op1_sign_reged && op2_sign_reged && ~over[32] : 0;
|
|
|
finish = 0;
|
finish = 0;
|
end
|
end
|
end
|
end
|
else if(start)
|
else if(start)
|
begin
|
begin
|
if(overflow)
|
if(overflow)
|
begin
|
begin
|
hilo[63:0] = {hilo[31:0],32'b0};
|
hilo[63:0] = {hilo[31:0],32'b0};
|
rdy = 1;
|
rdy = 1;
|
end
|
end
|
else if(!count[5])
|
else if(!count[5])
|
begin
|
begin
|
if(mul)
|
if(mul)
|
begin
|
begin
|
if(sign)
|
if(sign)
|
begin
|
begin
|
case({hilo[0],sub_or_yn})
|
case({hilo[0],sub_or_yn})
|
2'b10:hilo[64:32] = hilo[64:32] + nop2_reged;
|
2'b10:hilo[64:32] = hilo[64:32] + nop2_reged;
|
2'b01:hilo[64:32] = hilo[64:32] + op2_reged;
|
2'b01:hilo[64:32] = hilo[64:32] + op2_reged;
|
default:;
|
default:;
|
endcase
|
endcase
|
{hilo[63:0],sub_or_yn} = hilo[64:0];
|
{hilo[63:0],sub_or_yn} = hilo[64:0];
|
end
|
end
|
else begin
|
else begin
|
if(hilo[0]) hilo[64:32] = hilo[64:32] + op2_reged;
|
if(hilo[0]) hilo[64:32] = hilo[64:32] + op2_reged;
|
hilo = {1'b0,hilo[64:1]};
|
hilo = {1'b0,hilo[64:1]};
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
sub_or_yn = hilo[64]== op2_sign_reged;
|
sub_or_yn = hilo[64]== op2_sign_reged;
|
hilo[64:1] = hilo[63:0];
|
hilo[64:1] = hilo[63:0];
|
|
|
hilo[64:32] = sub_or_yn ? hilo[64:32] + nop2_reged : hilo[64:32] + op2_reged;
|
hilo[64:32] = sub_or_yn ? hilo[64:32] + nop2_reged : hilo[64:32] + op2_reged;
|
|
|
hilo[0] = hilo[64]== op2_sign_reged;
|
hilo[0] = hilo[64]== op2_sign_reged;
|
end
|
end
|
|
|
count = count + 1'b1;
|
count = count + 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if(finish)
|
if(finish)
|
begin
|
begin
|
if(add1) hilo[31:0] = hilo[31:0] + 1;
|
if(add1) hilo[31:0] = hilo[31:0] + 1;
|
case({addop2,addnop2})
|
case({addop2,addnop2})
|
2'b10: hilo[64:32] = hilo[64:32] + op2_reged;
|
2'b10: hilo[64:32] = hilo[64:32] + op2_reged;
|
2'b01: hilo[64:32] = hilo[64:32] + nop2_reged;
|
2'b01: hilo[64:32] = hilo[64:32] + nop2_reged;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
rdy = 1;
|
rdy = 1;
|
end
|
end
|
else begin
|
else begin
|
{add1,addop2,addnop2} = 3'b000;
|
{add1,addop2,addnop2} = 3'b000;
|
finish = 1;
|
finish = 1;
|
|
|
if(~mul)
|
if(~mul)
|
begin:LAST_CYCLE_DEAL_SECTION
|
begin:LAST_CYCLE_DEAL_SECTION
|
reg eqz,eqop2,eqnop2;
|
reg eqz,eqop2,eqnop2;
|
eqz = hilo[64:32] == 0;
|
eqz = hilo[64:32] == 0;
|
eqop2 = hilo[64:32] == op2_reged;
|
eqop2 = hilo[64:32] == op2_reged;
|
eqnop2 = hilo[64:32] == nop2_reged;
|
eqnop2 = hilo[64:32] == nop2_reged;
|
casex({op1_sign_reged,op2_sign_reged,eqz,eqop2,eqnop2})
|
casex({op1_sign_reged,op2_sign_reged,eqz,eqop2,eqnop2})
|
5'b101xx : {add1,addop2,addnop2} = 3'b000;
|
5'b101xx : {add1,addop2,addnop2} = 3'b000;
|
5'b100x1 : {add1,addop2,addnop2} = 3'b010;
|
5'b100x1 : {add1,addop2,addnop2} = 3'b010;
|
5'b111xx : {add1,addop2,addnop2} = 3'b100;
|
5'b111xx : {add1,addop2,addnop2} = 3'b100;
|
5'b1101x : {add1,addop2,addnop2} = 3'b101;
|
5'b1101x : {add1,addop2,addnop2} = 3'b101;
|
default :
|
default :
|
begin:LAST_CYCLE_DEAL_SECTION_DEFAULT
|
begin:LAST_CYCLE_DEAL_SECTION_DEFAULT
|
|
|
reg op1s_eq_op2s,op1s_eq_h64;
|
reg op1s_eq_op2s,op1s_eq_h64;
|
op1s_eq_op2s = op1_sign_reged == op2_sign_reged;
|
op1s_eq_op2s = op1_sign_reged == op2_sign_reged;
|
op1s_eq_h64 = op1_sign_reged == hilo[64];
|
op1s_eq_h64 = op1_sign_reged == hilo[64];
|
|
|
add1 = ~op1s_eq_op2s;
|
add1 = ~op1s_eq_op2s;
|
case({op1s_eq_op2s,op1s_eq_h64})//synthesis parallel_case
|
case({op1s_eq_op2s,op1s_eq_h64})//synthesis parallel_case
|
2'b00: {addop2,addnop2} = 2'b01;
|
2'b00: {addop2,addnop2} = 2'b01;
|
2'b10: {addop2,addnop2} = 2'b10;
|
2'b10: {addop2,addnop2} = 2'b10;
|
default: {addop2,addnop2} = 2'b00;
|
default: {addop2,addnop2} = 2'b00;
|
endcase
|
endcase
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
endmodule
|
endmodule
|
|
|
|
|
|
|