/******************************************************************
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/******************************************************************
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* *
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* *
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* Author: Liwei *
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* Author: Liwei *
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* *
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* *
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* This file is part of the "mips789" project. *
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* This file is part of the "mips789" project. *
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* Downloaded from: *
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* Downloaded from: *
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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* http://www.opencores.org/pdownloads.cgi/list/mips789 *
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* *
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* *
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* If you encountered any problem, please contact me via *
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* If you encountered any problem, please contact me via *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* Email:mcupro@opencores.org or mcupro@163.com *
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* *
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* *
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******************************************************************/
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******************************************************************/
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`include "mips789_defs.v"
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`include "mips789_defs.v"
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module rxd_d(input clr,input clk,input d,output reg q );
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module rxd_d(input clr,input clk,input d,output reg q );
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always @(posedge clk)
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always @(posedge clk)
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if (clr) q<=0;
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if (clr) q<=0;
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else q<=d|q;
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else q<=d|q;
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endmodule
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endmodule
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module uart0 (
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module uart0 (
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clk,rst,rxd_ft,ser_rxd,txd_ld,
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clk,rst,rxd_ft,ser_rxd,txd_ld,
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din,rxd_rdy,ser_txd,txd_busy,dout) ;
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din,rxd_rdy,ser_txd,txd_busy,dout) ;
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input clk;
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input clk;
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wire clk;
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wire clk;
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input rst;
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input rst;
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wire rst;
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wire rst;
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input rxd_ft;
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input rxd_ft;
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wire rxd_ft;
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wire rxd_ft;
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input ser_rxd;
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input ser_rxd;
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wire ser_rxd;
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wire ser_rxd;
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input txd_ld;
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input txd_ld;
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wire txd_ld;
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wire txd_ld;
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input [7:0] din;
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input [7:0] din;
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wire [7:0] din;
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wire [7:0] din;
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output rxd_rdy;
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output rxd_rdy;
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wire rxd_rdy;
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wire rxd_rdy;
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output ser_txd;
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output ser_txd;
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wire ser_txd;
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wire ser_txd;
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output txd_busy;
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output txd_busy;
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wire txd_busy;
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wire txd_busy;
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output [7:0] dout;
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output [7:0] dout;
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wire [7:0] dout;
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wire [7:0] dout;
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wire clk_uart=clk;
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wire clk_uart=clk;
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wire w_rxd_rdy;
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wire w_rxd_rdy;
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uart_read uart_rd_tak(
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uart_read uart_rd_tak(
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.sync_reset(rst),
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.sync_reset(rst),
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.clk(clk),
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.clk(clk),
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.rxd(ser_rxd),
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.rxd(ser_rxd),
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.buffer_reg(dout),
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.buffer_reg(dout),
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.int_req(w_rxd_rdy)
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.int_req(w_rxd_rdy)
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);
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);
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rxd_d rxd_rdy_hold_lw
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rxd_d rxd_rdy_hold_lw
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(
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(
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.clk(clk_uart),
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.clk(clk_uart),
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.clr(rxd_ft),
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.clr(rxd_ft),
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.d(w_rxd_rdy),
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.d(w_rxd_rdy),
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.q(rxd_rdy)
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.q(rxd_rdy)
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);
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);
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uart_write uart_txd
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uart_write uart_txd
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(
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(
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.sync_reset(rst),
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.sync_reset(rst),
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.clk(clk),
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.clk(clk),
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.txd(ser_txd),
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.txd(ser_txd),
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.data_in(din) ,
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.data_in(din) ,
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.write_request(txd_ld),
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.write_request(txd_ld),
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//.write_done(),
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//.write_done(),
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.write_busy(txd_busy)
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.write_busy(txd_busy)
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);
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);
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endmodule
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endmodule
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//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores.
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//These modules below are modified slight by Liwei based on YACC,an CPU core in opencores.
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//Thank you TAK
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//Thank you TAK
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module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
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module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
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input sync_reset,clk;
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input sync_reset,clk;
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input [7:0] data_in;
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input [7:0] data_in;
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input write_request;
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input write_request;
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output txd,write_done;
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output txd,write_done;
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output write_busy;
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output write_busy;
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wire queue_full;
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wire queue_full;
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wire queing, read_request;
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wire queing, read_request;
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wire [7:0] queue_data;
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wire [7:0] queue_data;
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reg read_request_ff;
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reg read_request_ff;
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//________|--|___write_request (upper module : its period should be 1clock time.)
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//________|--|___write_request (upper module : its period should be 1clock time.)
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//__________________________|-|______write_done (Responds by this module posedge interrupt)
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//__________________________|-|______write_done (Responds by this module posedge interrupt)
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//With 512Bytes FIFO.
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//With 512Bytes FIFO.
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//No error handling is supported.
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//No error handling is supported.
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reg [15:0] clk_ctr;//liwei
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reg [15:0] clk_ctr;//liwei
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reg [2:0] bit_ctr;
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reg [2:0] bit_ctr;
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reg [2:0] ua_state;
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reg [2:0] ua_state;
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reg [7:0] tx_sr;
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reg [7:0] tx_sr;
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reg txd;
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reg txd;
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wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
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wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
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clk_ctr_enable_state, bit_ctr_enable_state ;
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clk_ctr_enable_state, bit_ctr_enable_state ;
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wire tx_state;
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wire tx_state;
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wire empty;
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wire empty;
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assign write_busy=queue_full;//Apr.2.2005
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assign write_busy=queue_full;//Apr.2.2005
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (~sync_reset) read_request_ff<=1'b0;
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if (~sync_reset) read_request_ff<=1'b0;
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else read_request_ff<=read_request;
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else read_request_ff<=read_request;
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end
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end
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assign queing= !empty;
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assign queing= !empty;
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assign read_request = queing && ua_state==3'b000;//Jul.14.2004
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assign read_request = queing && ua_state==3'b000;//Jul.14.2004
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assign write_done=ua_state==3'b101;
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assign write_done=ua_state==3'b101;
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`ifdef ALTERA
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`ifdef ALTERA
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fifo512_cyclone alt_fifo(
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fifo512_cyclone alt_fifo(
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.data(data_in),
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.data(data_in),
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.wrreq(write_request),
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.wrreq(write_request),
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.rdreq(read_request),
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.rdreq(read_request),
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.clock(clk),
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.clock(clk),
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.q(queue_data),
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.q(queue_data),
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.full(queue_full),
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.full(queue_full),
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.empty(empty));
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.empty(empty));
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`else//debug model in simulations
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`else//debug model in simulations
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sim_fifo512_cyclone sim_fifo(
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sim_fifo512_cyclone sim_fifo(
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.data(data_in),
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.data(data_in),
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.wrreq(write_request),
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.wrreq(write_request),
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.rdreq(read_request),
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.rdreq(read_request),
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.clock(clk),
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.clock(clk),
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.q(queue_data),
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.q(queue_data),
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.full(queue_full),
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.full(queue_full),
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.empty(empty),
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.empty(empty),
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.rst(sync_reset));
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.rst(sync_reset));
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`endif
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`endif
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// 7bit counter
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// 7bit counter
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// I set the regerster lenth as 16 .Sufficent but not waste.Liwei
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// I set the regerster lenth as 16 .Sufficent but not waste.Liwei
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset)
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if (~sync_reset)
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clk_ctr <= 0;
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clk_ctr <= 0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else clk_ctr <= 0;
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else clk_ctr <= 0;
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end
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end
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assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
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assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
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assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
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assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
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// 3bit counter
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// 3bit counter
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (~sync_reset)
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if (~sync_reset)
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bit_ctr <= 0;
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bit_ctr <= 0;
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else if (bit_ctr_enable_state) begin
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else if (bit_ctr_enable_state) begin
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if (clk_ctr_equ15)
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if (clk_ctr_equ15)
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bit_ctr <= bit_ctr + 1;
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bit_ctr <= bit_ctr + 1;
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end
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end
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else
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else
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bit_ctr <= 0;
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bit_ctr <= 0;
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end
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end
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assign bit_ctr_equ7 = (bit_ctr==7);
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assign bit_ctr_equ7 = (bit_ctr==7);
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assign clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 || ua_state==3'b001 || ua_state==3'b100||ua_state==3'b101;
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assign clk_ctr_enable_state = bit_ctr_enable_state ||ua_state==3'b110 || ua_state==3'b001 || ua_state==3'b100||ua_state==3'b101;
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assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011;
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assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011;
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) ua_state <= 3'b000;
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if (~sync_reset) ua_state <= 3'b000;
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else begin
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else begin
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case (ua_state)
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case (ua_state)
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3'b000: if (queing) ua_state <= 3'b001; //wait write_request
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3'b000: if (queing) ua_state <= 3'b001; //wait write_request
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3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
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3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
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3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
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3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
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3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send
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3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send
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3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send
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3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send
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3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit send
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3'b101: if (clk_ctr_equ15) ua_state <= 3'b110; //LIWEI // stop bit send
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3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI
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3'b110: if (clk_ctr_equ15) ua_state <= 3'b111; //LIWEI
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3'b111: ua_state <= 3'h0; // TAK // byte read cycle end
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3'b111: ua_state <= 3'h0; // TAK // byte read cycle end
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default: ua_state <= 3'h0;
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default: ua_state <= 3'h0;
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endcase
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endcase
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end
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end
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end
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end
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// tx shift reg.
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// tx shift reg.
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) tx_sr<=0;
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if (~sync_reset) tx_sr<=0;
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else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
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else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
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else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
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else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
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end
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end
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assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15;
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assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15;
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// tx
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// tx
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) txd <=1'b1;
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if (~sync_reset) txd <=1'b1;
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else if (~sync_reset) txd<=1'b1;
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else if (~sync_reset) txd<=1'b1;
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else if (ua_state==3'h0) txd<=1'b1;
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else if (ua_state==3'h0) txd<=1'b1;
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else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit
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else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit
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else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
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else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
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else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit
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else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit
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end
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end
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endmodule
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endmodule
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module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
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module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
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input sync_reset;
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input sync_reset;
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input clk, rxd;
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input clk, rxd;
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output [7:0] buffer_reg;
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output [7:0] buffer_reg;
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output int_req;
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output int_req;
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//________|-|______int_req (This module,, posedge interrupt)
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//________|-|______int_req (This module,, posedge interrupt)
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//
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//
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//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
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//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
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//
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//
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//No error handling (overrun ) is supported.
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//No error handling (overrun ) is supported.
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reg rxq1;
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reg rxq1;
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reg [15:0] clk_ctr;
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reg [15:0] clk_ctr;
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reg [2:0] bit_ctr;
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reg [2:0] bit_ctr;
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reg [2:0] ua_state;
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reg [2:0] ua_state;
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reg [7:0] rx_sr; //.,tx_sr;
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reg [7:0] rx_sr; //.,tx_sr;
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reg int_req;
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reg int_req;
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reg [7:0] buffer_reg;
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reg [7:0] buffer_reg;
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wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
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wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
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clk_ctr_enable_state, bit_ctr_enable_state ;
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clk_ctr_enable_state, bit_ctr_enable_state ;
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wire clk_ctr_equ0;
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wire clk_ctr_equ0;
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//sync_reset
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//sync_reset
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//synchronization
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//synchronization
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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rxq1 <=rxd ;
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rxq1 <=rxd ;
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end
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end
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// 7bit counter
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// 7bit counter
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset)
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if (~sync_reset)
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clk_ctr <= 0;
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clk_ctr <= 0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
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else clk_ctr <= 0;
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else clk_ctr <= 0;
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end
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end
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assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
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assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
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assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
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assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
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assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
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assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
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// 3bit counter
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// 3bit counter
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (~sync_reset)
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if (~sync_reset)
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bit_ctr <= 0;
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bit_ctr <= 0;
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else if (bit_ctr_enable_state) begin
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else if (bit_ctr_enable_state) begin
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if (clk_ctr_equ15)
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if (clk_ctr_equ15)
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bit_ctr <= bit_ctr + 1;
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bit_ctr <= bit_ctr + 1;
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end
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end
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else
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else
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bit_ctr <= 0;
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bit_ctr <= 0;
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end
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end
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assign bit_ctr_equ7 = (bit_ctr==7);
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assign bit_ctr_equ7 = (bit_ctr==7);
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assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
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assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
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assign bit_ctr_enable_state = ua_state==3'h2;
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assign bit_ctr_enable_state = ua_state==3'h2;
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) ua_state <= 3'h0;
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if (~sync_reset) ua_state <= 3'h0;
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else begin
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else begin
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case (ua_state)
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case (ua_state)
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3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
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3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
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3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
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3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
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3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
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3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
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3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive
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3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive
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3'h4: ua_state <= 3'b000;
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3'h4: ua_state <= 3'b000;
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default: ua_state <= 3'b000;
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default: ua_state <= 3'b000;
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endcase
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endcase
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end
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end
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end
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end
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//reg_we
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//reg_we
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) buffer_reg<=8'h00;
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if (~sync_reset) buffer_reg<=8'h00;
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else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
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else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
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end
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end
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//int_req
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//int_req
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) int_req<=1'b0;
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if (~sync_reset) int_req<=1'b0;
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else if (ua_state==3'h4 ) int_req<=1'b1;
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else if (ua_state==3'h4 ) int_req<=1'b1;
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else int_req<=1'b0;
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else int_req<=1'b0;
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end
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end
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|
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// rx shift reg.
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// rx shift reg.
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always @(posedge clk ) begin
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always @(posedge clk ) begin
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if (~sync_reset) rx_sr <= 0;
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if (~sync_reset) rx_sr <= 0;
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else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
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else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
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end
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end
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|
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endmodule
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endmodule
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