# ##############################################################################
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# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
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# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
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# Fri Jun 22 12:14:26 2007
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# Fri Jun 22 12:14:26 2007
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# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
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# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
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# Family: virtex2p
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# Family: virtex2p
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# Device: xc2vp30
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# Device: xc2vp30
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# Package: ff896
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# Package: ff896
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# Speed Grade: -7
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# Speed Grade: -7
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# Processor: PPC 405
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# Processor: PPC 405
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# Processor clock frequency: 100.000000 MHz
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# Processor clock frequency: 100.000000 MHz
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# Bus clock frequency: 100.000000 MHz
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# Bus clock frequency: 100.000000 MHz
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# Debug interface: FPGA JTAG
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# Debug interface: FPGA JTAG
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# On Chip Memory : 128 KB
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# On Chip Memory : 128 KB
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# Total Off Chip Memory : 512 MB
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# Total Off Chip Memory : 512 MB
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# - DDR_SDRAM_64Mx64 Dual Rank = 256 MB
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# - DDR_SDRAM_64Mx64 Dual Rank = 256 MB
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# - DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 = 256 MB
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# - DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 = 256 MB
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# ##############################################################################
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# ##############################################################################
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PARAMETER VERSION = 2.1.0
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PARAMETER VERSION = 2.1.0
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PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
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PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
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PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
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PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn, DIR = O
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn, DIR = O, VEC = [0:1]
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PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
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PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
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PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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PORT myipif_0_LEDs_pin = myipif_0_LEDs, DIR = O, VEC = [3:0]
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PORT myipif_0_LEDs_pin = myipif_0_LEDs, DIR = O, VEC = [3:0]
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PORT myipif_0_VGA_OUT_PIXEL_CLOCK_pin = myipif_0_VGA_OUT_PIXEL_CLOCK, DIR = O
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PORT myipif_0_VGA_OUT_PIXEL_CLOCK_pin = myipif_0_VGA_OUT_PIXEL_CLOCK, DIR = O
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PORT myipif_0_VGA_COMP_SYNCH_pin = myipif_0_VGA_COMP_SYNCH, DIR = O
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PORT myipif_0_VGA_COMP_SYNCH_pin = myipif_0_VGA_COMP_SYNCH, DIR = O
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PORT myipif_0_VGA_OUT_BLANK_Z_pin = myipif_0_VGA_OUT_BLANK_Z, DIR = O
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PORT myipif_0_VGA_OUT_BLANK_Z_pin = myipif_0_VGA_OUT_BLANK_Z, DIR = O
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PORT myipif_0_VGA_HSYNCH_pin = myipif_0_VGA_HSYNCH, DIR = O
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PORT myipif_0_VGA_HSYNCH_pin = myipif_0_VGA_HSYNCH, DIR = O
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PORT myipif_0_VGA_VSYNCH_pin = myipif_0_VGA_VSYNCH, DIR = O
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PORT myipif_0_VGA_VSYNCH_pin = myipif_0_VGA_VSYNCH, DIR = O
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PORT myipif_0_VGA_OUT_RED_pin = myipif_0_VGA_OUT_RED, DIR = O, VEC = [7:0]
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PORT myipif_0_VGA_OUT_RED_pin = myipif_0_VGA_OUT_RED, DIR = O, VEC = [7:0]
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PORT myipif_0_VGA_OUT_GREEN_pin = myipif_0_VGA_OUT_GREEN, DIR = O, VEC = [7:0]
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PORT myipif_0_VGA_OUT_GREEN_pin = myipif_0_VGA_OUT_GREEN, DIR = O, VEC = [7:0]
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PORT myipif_0_VGA_OUT_BLUE_pin = myipif_0_VGA_OUT_BLUE, DIR = O, VEC = [7:0]
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PORT myipif_0_VGA_OUT_BLUE_pin = myipif_0_VGA_OUT_BLUE, DIR = O, VEC = [7:0]
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PORT myipif_0_SWITCHEs_pin = myipif_0_SWITCHEs, DIR = I, VEC = [3:0]
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PORT myipif_0_SWITCHEs_pin = myipif_0_SWITCHEs, DIR = I, VEC = [3:0]
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PORT myipif_0_BUTTONs_pin = myipif_0_BUTTONs, DIR = I, VEC = [4:0]
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PORT myipif_0_BUTTONs_pin = myipif_0_BUTTONs, DIR = I, VEC = [4:0]
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BEGIN ppc405
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BEGIN ppc405
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PARAMETER INSTANCE = ppc405_0
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PARAMETER INSTANCE = ppc405_0
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PARAMETER HW_VER = 2.00.c
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PARAMETER HW_VER = 2.00.c
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BUS_INTERFACE IPLB = plb
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BUS_INTERFACE IPLB = plb
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BUS_INTERFACE DPLB = plb
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BUS_INTERFACE DPLB = plb
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BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC0
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BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC0
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PORT PLBCLK = sys_clk_s
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PORT PLBCLK = sys_clk_s
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PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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PORT RSTC405RESETCORE = RSTC405RESETCORE
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PORT RSTC405RESETCORE = RSTC405RESETCORE
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PORT RSTC405RESETSYS = RSTC405RESETSYS
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PORT RSTC405RESETSYS = RSTC405RESETSYS
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PORT CPMC405CLOCK = sys_clk_s
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PORT CPMC405CLOCK = sys_clk_s
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END
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END
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BEGIN jtagppc_cntlr
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BEGIN jtagppc_cntlr
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PARAMETER INSTANCE = jtagppc_0
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PARAMETER INSTANCE = jtagppc_0
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PARAMETER HW_VER = 2.00.a
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PARAMETER HW_VER = 2.00.a
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BUS_INTERFACE JTAGPPC0 = jtagppc_0_JTAGPPC0
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BUS_INTERFACE JTAGPPC0 = jtagppc_0_JTAGPPC0
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BUS_INTERFACE JTAGPPC1 = jtagppc_0_JTAGPPC1
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BUS_INTERFACE JTAGPPC1 = jtagppc_0_JTAGPPC1
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END
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END
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BEGIN proc_sys_reset
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BEGIN proc_sys_reset
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PARAMETER INSTANCE = reset_block
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PARAMETER INSTANCE = reset_block
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PARAMETER HW_VER = 1.00.a
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT Ext_Reset_In = sys_rst_s
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PORT Ext_Reset_In = sys_rst_s
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PORT Slowest_sync_clk = sys_clk_s
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PORT Slowest_sync_clk = sys_clk_s
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PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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PORT Core_Reset_Req = C405RSTCORERESETREQ
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PORT Core_Reset_Req = C405RSTCORERESETREQ
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PORT System_Reset_Req = C405RSTSYSRESETREQ
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PORT System_Reset_Req = C405RSTSYSRESETREQ
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PORT Rstc405resetchip = RSTC405RESETCHIP
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PORT Rstc405resetchip = RSTC405RESETCHIP
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PORT Rstc405resetcore = RSTC405RESETCORE
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PORT Rstc405resetcore = RSTC405RESETCORE
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PORT Rstc405resetsys = RSTC405RESETSYS
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PORT Rstc405resetsys = RSTC405RESETSYS
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PORT Bus_Struct_Reset = sys_bus_reset
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PORT Bus_Struct_Reset = sys_bus_reset
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PORT Dcm_locked = dcm_1_lock
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PORT Dcm_locked = dcm_1_lock
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END
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END
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BEGIN plb_v34
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BEGIN plb_v34
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PARAMETER INSTANCE = plb
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PARAMETER INSTANCE = plb
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PARAMETER HW_VER = 1.02.a
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PARAMETER HW_VER = 1.02.a
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_EXT_RESET_HIGH = 1
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT SYS_Rst = sys_bus_reset
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PORT SYS_Rst = sys_bus_reset
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PORT PLB_Clk = sys_clk_s
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PORT PLB_Clk = sys_clk_s
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END
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END
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BEGIN opb_v20
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BEGIN opb_v20
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PARAMETER INSTANCE = opb
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PARAMETER INSTANCE = opb
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PARAMETER HW_VER = 1.10.c
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PARAMETER HW_VER = 1.10.c
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PARAMETER C_EXT_RESET_HIGH = 1
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT SYS_Rst = sys_bus_reset
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PORT SYS_Rst = sys_bus_reset
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PORT OPB_Clk = sys_clk_s
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PORT OPB_Clk = sys_clk_s
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END
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END
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BEGIN plb2opb_bridge
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BEGIN plb2opb_bridge
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PARAMETER INSTANCE = plb2opb
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PARAMETER INSTANCE = plb2opb
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PARAMETER HW_VER = 1.01.a
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_NUM_ADDR_RNG = 1
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PARAMETER C_NUM_ADDR_RNG = 1
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PARAMETER C_RNG0_BASEADDR = 0x00000000
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PARAMETER C_RNG0_BASEADDR = 0x00000000
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PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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BUS_INTERFACE MOPB = opb
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BUS_INTERFACE MOPB = opb
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BUS_INTERFACE SPLB = plb
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BUS_INTERFACE SPLB = plb
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END
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END
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BEGIN opb_uartlite
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BEGIN opb_uartlite
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PARAMETER INSTANCE = RS232_Uart_1
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PARAMETER INSTANCE = RS232_Uart_1
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PARAMETER HW_VER = 1.00.b
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BAUDRATE = 9600
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PARAMETER C_BAUDRATE = 9600
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_ODD_PARITY = 0
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PARAMETER C_ODD_PARITY = 0
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_CLK_FREQ = 100000000
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PARAMETER C_CLK_FREQ = 100000000
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PARAMETER C_BASEADDR = 0x40600000
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PARAMETER C_BASEADDR = 0x40600000
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PARAMETER C_HIGHADDR = 0x4060ffff
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PARAMETER C_HIGHADDR = 0x4060ffff
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BUS_INTERFACE SOPB = opb
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BUS_INTERFACE SOPB = opb
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PORT RX = fpga_0_RS232_Uart_1_RX
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PORT RX = fpga_0_RS232_Uart_1_RX
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PORT TX = fpga_0_RS232_Uart_1_TX
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PORT TX = fpga_0_RS232_Uart_1_TX
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END
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END
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BEGIN opb_ddr
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BEGIN opb_ddr
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PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
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PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
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PARAMETER HW_VER = 2.00.c
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PARAMETER HW_VER = 2.00.c
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PARAMETER C_OPB_CLK_PERIOD_PS = 10000
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PARAMETER C_OPB_CLK_PERIOD_PS = 10000
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PARAMETER C_NUM_BANKS_MEM = 2
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PARAMETER C_NUM_BANKS_MEM = 2
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PARAMETER C_NUM_CLK_PAIRS = 4
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PARAMETER C_NUM_CLK_PAIRS = 4
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PARAMETER C_REG_DIMM = 0
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PARAMETER C_REG_DIMM = 0
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PARAMETER C_DDR_TMRD = 20000
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PARAMETER C_DDR_TMRD = 20000
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PARAMETER C_DDR_TWR = 20000
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PARAMETER C_DDR_TWR = 20000
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PARAMETER C_DDR_TRAS = 60000
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PARAMETER C_DDR_TRAS = 60000
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PARAMETER C_DDR_TRC = 90000
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PARAMETER C_DDR_TRC = 90000
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PARAMETER C_DDR_TRFC = 100000
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PARAMETER C_DDR_TRFC = 100000
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PARAMETER C_DDR_TRCD = 30000
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PARAMETER C_DDR_TRCD = 30000
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PARAMETER C_DDR_TRRD = 20000
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PARAMETER C_DDR_TRRD = 20000
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PARAMETER C_DDR_TRP = 30000
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PARAMETER C_DDR_TRP = 30000
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PARAMETER C_DDR_TREFC = 70300000
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PARAMETER C_DDR_TREFC = 70300000
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PARAMETER C_DDR_AWIDTH = 13
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PARAMETER C_DDR_AWIDTH = 13
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PARAMETER C_DDR_COL_AWIDTH = 10
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PARAMETER C_DDR_COL_AWIDTH = 10
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PARAMETER C_DDR_BANK_AWIDTH = 2
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PARAMETER C_DDR_BANK_AWIDTH = 2
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PARAMETER C_DDR_DWIDTH = 64
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PARAMETER C_DDR_DWIDTH = 64
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PARAMETER C_MEM0_BASEADDR = 0x00000000
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PARAMETER C_MEM0_BASEADDR = 0x00000000
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PARAMETER C_MEM0_HIGHADDR = 0x0fffffff
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PARAMETER C_MEM0_HIGHADDR = 0x0fffffff
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PARAMETER C_MEM1_BASEADDR = 0x10000000
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PARAMETER C_MEM1_BASEADDR = 0x10000000
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PARAMETER C_MEM1_HIGHADDR = 0x1fffffff
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PARAMETER C_MEM1_HIGHADDR = 0x1fffffff
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PARAMETER C_INCLUDE_BURST_SUPPORT = 1
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PARAMETER C_INCLUDE_BURST_SUPPORT = 1
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BUS_INTERFACE SOPB = opb
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BUS_INTERFACE SOPB = opb
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PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr
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PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr
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PORT DDR_BankAddr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr
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PORT DDR_BankAddr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr
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PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn
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PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn
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PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE
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PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE
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PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn
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PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn
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PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn
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PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn
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PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn
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PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn
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PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM
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PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM
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PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS
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PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS
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PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ
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PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ
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PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
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PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
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PORT DDR_Clkn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0
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PORT DDR_Clkn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0
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PORT Device_Clk90_in = clk_90_s
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PORT Device_Clk90_in = clk_90_s
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PORT Device_Clk90_in_n = clk_90_n_s
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PORT Device_Clk90_in_n = clk_90_n_s
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PORT Device_Clk = sys_clk_s
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PORT Device_Clk = sys_clk_s
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PORT Device_Clk_n = sys_clk_n_s
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PORT Device_Clk_n = sys_clk_n_s
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PORT DDR_Clk90_in = ddr_clk_90_s
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PORT DDR_Clk90_in = ddr_clk_90_s
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PORT DDR_Clk90_in_n = ddr_clk_90_n_s
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PORT DDR_Clk90_in_n = ddr_clk_90_n_s
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END
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END
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BEGIN plb_bram_if_cntlr
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BEGIN plb_bram_if_cntlr
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PARAMETER INSTANCE = plb_bram_if_cntlr_1
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PARAMETER INSTANCE = plb_bram_if_cntlr_1
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PARAMETER HW_VER = 1.00.b
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PARAMETER HW_VER = 1.00.b
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PARAMETER c_plb_clk_period_ps = 10000
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PARAMETER c_plb_clk_period_ps = 10000
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PARAMETER c_baseaddr = 0xfffe0000
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PARAMETER c_baseaddr = 0xfffe0000
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PARAMETER c_highaddr = 0xffffffff
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PARAMETER c_highaddr = 0xffffffff
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BUS_INTERFACE SPLB = plb
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BUS_INTERFACE SPLB = plb
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BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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END
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END
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BEGIN bram_block
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BEGIN bram_block
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PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
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PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
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PARAMETER HW_VER = 1.00.a
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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END
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END
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BEGIN util_vector_logic
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BEGIN util_vector_logic
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PARAMETER INSTANCE = sysclk_inv
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PARAMETER INSTANCE = sysclk_inv
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PARAMETER HW_VER = 1.00.a
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_SIZE = 1
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PARAMETER C_SIZE = 1
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PARAMETER C_OPERATION = not
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PARAMETER C_OPERATION = not
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PORT Op1 = sys_clk_s
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PORT Op1 = sys_clk_s
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PORT Res = sys_clk_n_s
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PORT Res = sys_clk_n_s
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END
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END
|
|
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BEGIN util_vector_logic
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BEGIN util_vector_logic
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PARAMETER INSTANCE = clk90_inv
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PARAMETER INSTANCE = clk90_inv
|
PARAMETER HW_VER = 1.00.a
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_SIZE = 1
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PARAMETER C_SIZE = 1
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PARAMETER C_OPERATION = not
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PARAMETER C_OPERATION = not
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PORT Op1 = clk_90_s
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PORT Op1 = clk_90_s
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PORT Res = clk_90_n_s
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PORT Res = clk_90_n_s
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END
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END
|
|
|
BEGIN util_vector_logic
|
BEGIN util_vector_logic
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PARAMETER INSTANCE = ddr_clk90_inv
|
PARAMETER INSTANCE = ddr_clk90_inv
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PARAMETER HW_VER = 1.00.a
|
PARAMETER HW_VER = 1.00.a
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PARAMETER C_SIZE = 1
|
PARAMETER C_SIZE = 1
|
PARAMETER C_OPERATION = not
|
PARAMETER C_OPERATION = not
|
PORT Op1 = ddr_clk_90_s
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PORT Op1 = ddr_clk_90_s
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PORT Res = ddr_clk_90_n_s
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PORT Res = ddr_clk_90_n_s
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END
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END
|
|
|
BEGIN dcm_module
|
BEGIN dcm_module
|
PARAMETER INSTANCE = dcm_0
|
PARAMETER INSTANCE = dcm_0
|
PARAMETER HW_VER = 1.00.a
|
PARAMETER HW_VER = 1.00.a
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PARAMETER C_CLK0_BUF = TRUE
|
PARAMETER C_CLK0_BUF = TRUE
|
PARAMETER C_CLK90_BUF = TRUE
|
PARAMETER C_CLK90_BUF = TRUE
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
PARAMETER C_CLK_FEEDBACK = 1X
|
PARAMETER C_CLK_FEEDBACK = 1X
|
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
PARAMETER C_EXT_RESET_HIGH = 1
|
PARAMETER C_EXT_RESET_HIGH = 1
|
PORT CLKIN = dcm_clk_s
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PORT CLKIN = dcm_clk_s
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PORT CLK0 = sys_clk_s
|
PORT CLK0 = sys_clk_s
|
PORT CLK90 = clk_90_s
|
PORT CLK90 = clk_90_s
|
PORT CLKFB = sys_clk_s
|
PORT CLKFB = sys_clk_s
|
PORT RST = net_gnd
|
PORT RST = net_gnd
|
PORT LOCKED = dcm_0_lock
|
PORT LOCKED = dcm_0_lock
|
END
|
END
|
|
|
BEGIN dcm_module
|
BEGIN dcm_module
|
PARAMETER INSTANCE = dcm_1
|
PARAMETER INSTANCE = dcm_1
|
PARAMETER HW_VER = 1.00.a
|
PARAMETER HW_VER = 1.00.a
|
PARAMETER C_CLK0_BUF = TRUE
|
PARAMETER C_CLK0_BUF = TRUE
|
PARAMETER C_CLK90_BUF = TRUE
|
PARAMETER C_CLK90_BUF = TRUE
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
PARAMETER C_CLKIN_PERIOD = 10.000000
|
PARAMETER C_CLK_FEEDBACK = 1X
|
PARAMETER C_CLK_FEEDBACK = 1X
|
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
PARAMETER C_DLL_FREQUENCY_MODE = LOW
|
PARAMETER C_PHASE_SHIFT = 60
|
PARAMETER C_PHASE_SHIFT = 60
|
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
|
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
|
PARAMETER C_EXT_RESET_HIGH = 0
|
PARAMETER C_EXT_RESET_HIGH = 0
|
PORT CLKIN = ddr_feedback_s
|
PORT CLKIN = ddr_feedback_s
|
PORT CLK90 = ddr_clk_90_s
|
PORT CLK90 = ddr_clk_90_s
|
PORT CLK0 = dcm_1_FB
|
PORT CLK0 = dcm_1_FB
|
PORT CLKFB = dcm_1_FB
|
PORT CLKFB = dcm_1_FB
|
PORT RST = dcm_0_lock
|
PORT RST = dcm_0_lock
|
PORT LOCKED = dcm_1_lock
|
PORT LOCKED = dcm_1_lock
|
END
|
END
|
|
|
BEGIN myipif
|
BEGIN myipif
|
PARAMETER INSTANCE = myipif_0
|
PARAMETER INSTANCE = myipif_0
|
PARAMETER C_BASEADDR = 0x50000000
|
PARAMETER C_BASEADDR = 0x50000000
|
PARAMETER C_HIGHADDR = 0x5000FFFF
|
PARAMETER C_HIGHADDR = 0x5000FFFF
|
BUS_INTERFACE MSOPB = opb
|
BUS_INTERFACE MSOPB = opb
|
PORT LEDs = myipif_0_LEDs
|
PORT LEDs = myipif_0_LEDs
|
PORT BUTTONs = myipif_0_BUTTONs
|
PORT BUTTONs = myipif_0_BUTTONs
|
PORT SWITCHEs = myipif_0_SWITCHEs
|
PORT SWITCHEs = myipif_0_SWITCHEs
|
PORT VGA_OUT_PIXEL_CLOCK = myipif_0_VGA_OUT_PIXEL_CLOCK
|
PORT VGA_OUT_PIXEL_CLOCK = myipif_0_VGA_OUT_PIXEL_CLOCK
|
PORT VGA_COMP_SYNCH = myipif_0_VGA_COMP_SYNCH
|
PORT VGA_COMP_SYNCH = myipif_0_VGA_COMP_SYNCH
|
PORT VGA_OUT_BLANK_Z = myipif_0_VGA_OUT_BLANK_Z
|
PORT VGA_OUT_BLANK_Z = myipif_0_VGA_OUT_BLANK_Z
|
PORT VGA_HSYNCH = myipif_0_VGA_HSYNCH
|
PORT VGA_HSYNCH = myipif_0_VGA_HSYNCH
|
PORT VGA_VSYNCH = myipif_0_VGA_VSYNCH
|
PORT VGA_VSYNCH = myipif_0_VGA_VSYNCH
|
PORT VGA_OUT_RED = myipif_0_VGA_OUT_RED
|
PORT VGA_OUT_RED = myipif_0_VGA_OUT_RED
|
PORT VGA_OUT_GREEN = myipif_0_VGA_OUT_GREEN
|
PORT VGA_OUT_GREEN = myipif_0_VGA_OUT_GREEN
|
PORT VGA_OUT_BLUE = myipif_0_VGA_OUT_BLUE
|
PORT VGA_OUT_BLUE = myipif_0_VGA_OUT_BLUE
|
END
|
END
|
|
|
BEGIN ppc405
|
BEGIN ppc405
|
PARAMETER INSTANCE = ppc405_1
|
PARAMETER INSTANCE = ppc405_1
|
PARAMETER HW_VER = 2.00.c
|
PARAMETER HW_VER = 2.00.c
|
BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC1
|
BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC1
|
END
|
END
|
|
|
|
|