-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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-- File Name : JFIFGen.vhd
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-- File Name : JFIFGen.vhd
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--
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--
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-- Project : JPEG_ENC
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-- Project : JPEG_ENC
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--
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--
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-- Module : JFIFGen
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-- Module : JFIFGen
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--
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--
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-- Content : JFIF Header Generator
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-- Content : JFIF Header Generator
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--
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--
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-- Description :
|
-- Description :
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--
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--
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-- Spec. :
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-- Spec. :
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--
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--
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-- Author : Michal Krepa
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-- Author : Michal Krepa
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-- History :
|
-- History :
|
-- 20090309: (MK): Initial Creation.
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-- 20090309: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
----------------------------------- LIBRARY/PACKAGE ---------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
|
-- generic packages/libraries:
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
|
library work;
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library work;
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use work.JPEG_PKG.all;
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use work.JPEG_PKG.all;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-- user packages/libraries:
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity JFIFGen is
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entity JFIFGen is
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port
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port
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(
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(
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CLK : in std_logic;
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CLK : in std_logic;
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RST : in std_logic;
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RST : in std_logic;
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-- CTRL
|
-- CTRL
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start : in std_logic;
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start : in std_logic;
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ready : out std_logic;
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ready : out std_logic;
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eoi : in std_logic;
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eoi : in std_logic;
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|
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-- ByteStuffer
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-- ByteStuffer
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num_enc_bytes : in std_logic_vector(23 downto 0);
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num_enc_bytes : in std_logic_vector(23 downto 0);
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|
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-- HOST IF
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-- HOST IF
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qwren : in std_logic;
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qwren : in std_logic;
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qwaddr : in std_logic_vector(6 downto 0);
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qwaddr : in std_logic_vector(6 downto 0);
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qwdata : in std_logic_vector(7 downto 0);
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qwdata : in std_logic_vector(7 downto 0);
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image_size_reg : in std_logic_vector(31 downto 0);
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image_size_reg : in std_logic_vector(31 downto 0);
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image_size_reg_wr : in std_logic;
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image_size_reg_wr : in std_logic;
|
|
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-- OUT RAM
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-- OUT RAM
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ram_byte : out std_logic_vector(7 downto 0);
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ram_byte : out std_logic_vector(7 downto 0);
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ram_wren : out std_logic;
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ram_wren : out std_logic;
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ram_wraddr : out std_logic_vector(23 downto 0)
|
ram_wraddr : out std_logic_vector(23 downto 0)
|
);
|
);
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end entity JFIFGen;
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end entity JFIFGen;
|
|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
|
----------------------------------- ARCHITECTURE ------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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architecture RTL of JFIFGen is
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architecture RTL of JFIFGen is
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|
|
constant C_SIZE_Y_H : integer := 25;
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constant C_SIZE_Y_H : integer := 25;
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constant C_SIZE_Y_L : integer := 26;
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constant C_SIZE_Y_L : integer := 26;
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constant C_SIZE_X_H : integer := 27;
|
constant C_SIZE_X_H : integer := 27;
|
constant C_SIZE_X_L : integer := 28;
|
constant C_SIZE_X_L : integer := 28;
|
|
|
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
|
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
|
constant C_QLUM_BASE : integer := 44;
|
constant C_QLUM_BASE : integer := 44;
|
constant C_QCHR_BASE : integer := 44+69;
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constant C_QCHR_BASE : integer := 44+69;
|
|
|
|
|
signal hr_data : std_logic_vector(7 downto 0);
|
signal hr_data : std_logic_vector(7 downto 0);
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signal hr_waddr : std_logic_vector(9 downto 0);
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signal hr_waddr : std_logic_vector(9 downto 0);
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signal hr_raddr : std_logic_vector(9 downto 0);
|
signal hr_raddr : std_logic_vector(9 downto 0);
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signal hr_we : std_logic;
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signal hr_we : std_logic;
|
signal hr_q : std_logic_vector(7 downto 0);
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signal hr_q : std_logic_vector(7 downto 0);
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signal size_wr_cnt : unsigned(2 downto 0);
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signal size_wr_cnt : unsigned(2 downto 0);
|
signal size_wr : std_logic;
|
signal size_wr : std_logic;
|
signal rd_cnt : unsigned(9 downto 0);
|
signal rd_cnt : unsigned(9 downto 0);
|
signal rd_en : std_logic;
|
signal rd_en : std_logic;
|
signal rd_en_d1 : std_logic;
|
signal rd_en_d1 : std_logic;
|
signal rd_cnt_d1 : unsigned(rd_cnt'range);
|
signal rd_cnt_d1 : unsigned(rd_cnt'range);
|
signal rd_cnt_d2 : unsigned(rd_cnt'range);
|
signal rd_cnt_d2 : unsigned(rd_cnt'range);
|
signal eoi_cnt : unsigned(1 downto 0);
|
signal eoi_cnt : unsigned(1 downto 0);
|
signal eoi_wr : std_logic;
|
signal eoi_wr : std_logic;
|
signal eoi_wr_d1 : std_logic;
|
signal eoi_wr_d1 : std_logic;
|
|
|
component HeaderRam is
|
component HeaderRam is
|
port
|
port
|
(
|
(
|
d : in STD_LOGIC_VECTOR(7 downto 0);
|
d : in STD_LOGIC_VECTOR(7 downto 0);
|
waddr : in STD_LOGIC_VECTOR(9 downto 0);
|
waddr : in STD_LOGIC_VECTOR(9 downto 0);
|
raddr : in STD_LOGIC_VECTOR(9 downto 0);
|
raddr : in STD_LOGIC_VECTOR(9 downto 0);
|
we : in STD_LOGIC;
|
we : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
|
|
q : out STD_LOGIC_VECTOR(7 downto 0)
|
q : out STD_LOGIC_VECTOR(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture: begin
|
-- Architecture: begin
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
begin
|
begin
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- Header RAM
|
-- Header RAM
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
U_Header_RAM : entity work.HeaderRam
|
U_Header_RAM : HeaderRam
|
port map
|
port map
|
(
|
(
|
d => hr_data,
|
d => hr_data,
|
waddr => hr_waddr,
|
waddr => hr_waddr,
|
raddr => hr_raddr,
|
raddr => hr_raddr,
|
we => hr_we,
|
we => hr_we,
|
clk => CLK,
|
clk => CLK,
|
|
|
q => hr_q
|
q => hr_q
|
);
|
);
|
|
|
hr_raddr <= std_logic_vector(rd_cnt);
|
hr_raddr <= std_logic_vector(rd_cnt);
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- Host programming
|
-- Host programming
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
p_host_wr : process(CLK, RST)
|
p_host_wr : process(CLK, RST)
|
begin
|
begin
|
if RST = '1' then
|
if RST = '1' then
|
size_wr_cnt <= (others => '0');
|
size_wr_cnt <= (others => '0');
|
size_wr <= '0';
|
size_wr <= '0';
|
hr_we <= '0';
|
hr_we <= '0';
|
hr_data <= (others => '0');
|
hr_data <= (others => '0');
|
hr_waddr <= (others => '0');
|
hr_waddr <= (others => '0');
|
elsif CLK'event and CLK = '1' then
|
elsif CLK'event and CLK = '1' then
|
hr_we <= '0';
|
hr_we <= '0';
|
|
|
if image_size_reg_wr = '1' then
|
if image_size_reg_wr = '1' then
|
size_wr_cnt <= (others => '0');
|
size_wr_cnt <= (others => '0');
|
size_wr <= '1';
|
size_wr <= '1';
|
end if;
|
end if;
|
|
|
-- write image size
|
-- write image size
|
if size_wr = '1' then
|
if size_wr = '1' then
|
if size_wr_cnt = 4 then
|
if size_wr_cnt = 4 then
|
size_wr_cnt <= (others => '0');
|
size_wr_cnt <= (others => '0');
|
size_wr <= '0';
|
size_wr <= '0';
|
else
|
else
|
size_wr_cnt <= size_wr_cnt + 1;
|
size_wr_cnt <= size_wr_cnt + 1;
|
hr_we <= '1';
|
hr_we <= '1';
|
case size_wr_cnt is
|
case size_wr_cnt is
|
-- height H byte
|
-- height H byte
|
when "000" =>
|
when "000" =>
|
hr_data <= image_size_reg(15 downto 8);
|
hr_data <= image_size_reg(15 downto 8);
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
|
-- height L byte
|
-- height L byte
|
when "001" =>
|
when "001" =>
|
hr_data <= image_size_reg(7 downto 0);
|
hr_data <= image_size_reg(7 downto 0);
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
|
-- width H byte
|
-- width H byte
|
when "010" =>
|
when "010" =>
|
hr_data <= image_size_reg(31 downto 24);
|
hr_data <= image_size_reg(31 downto 24);
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
|
-- width L byte
|
-- width L byte
|
when "011" =>
|
when "011" =>
|
hr_data <= image_size_reg(23 downto 16);
|
hr_data <= image_size_reg(23 downto 16);
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
|
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
-- write Quantization table
|
-- write Quantization table
|
elsif qwren = '1' then
|
elsif qwren = '1' then
|
-- luminance table select
|
-- luminance table select
|
if qwaddr(6) = '0' then
|
if qwaddr(6) = '0' then
|
hr_waddr <= std_logic_vector
|
hr_waddr <= std_logic_vector
|
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
|
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
|
to_unsigned(C_QLUM_BASE,hr_waddr'length));
|
to_unsigned(C_QLUM_BASE,hr_waddr'length));
|
else
|
else
|
-- chrominance table select
|
-- chrominance table select
|
hr_waddr <= std_logic_vector
|
hr_waddr <= std_logic_vector
|
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
|
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
|
to_unsigned(C_QCHR_BASE,hr_waddr'length));
|
to_unsigned(C_QCHR_BASE,hr_waddr'length));
|
end if;
|
end if;
|
hr_we <= '1';
|
hr_we <= '1';
|
hr_data <= qwdata;
|
hr_data <= qwdata;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- CTRL
|
-- CTRL
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
p_ctrl : process(CLK, RST)
|
p_ctrl : process(CLK, RST)
|
begin
|
begin
|
if RST = '1' then
|
if RST = '1' then
|
ready <= '0';
|
ready <= '0';
|
rd_en <= '0';
|
rd_en <= '0';
|
rd_cnt <= (others => '0');
|
rd_cnt <= (others => '0');
|
rd_cnt_d1 <= (others => '0');
|
rd_cnt_d1 <= (others => '0');
|
rd_cnt_d2 <= (others => '0');
|
rd_cnt_d2 <= (others => '0');
|
rd_cnt_d1 <= (others => '0');
|
rd_cnt_d1 <= (others => '0');
|
rd_en_d1 <= '0';
|
rd_en_d1 <= '0';
|
eoi_wr_d1 <= '0';
|
eoi_wr_d1 <= '0';
|
eoi_wr <= '0';
|
eoi_wr <= '0';
|
eoi_cnt <= (others => '0');
|
eoi_cnt <= (others => '0');
|
ram_wren <= '0';
|
ram_wren <= '0';
|
ram_byte <= (others => '0');
|
ram_byte <= (others => '0');
|
ram_wraddr <= (others => '0');
|
ram_wraddr <= (others => '0');
|
elsif CLK'event and CLK = '1' then
|
elsif CLK'event and CLK = '1' then
|
ready <= '0';
|
ready <= '0';
|
rd_cnt_d1 <= rd_cnt;
|
rd_cnt_d1 <= rd_cnt;
|
rd_cnt_d2 <= rd_cnt_d1;
|
rd_cnt_d2 <= rd_cnt_d1;
|
rd_en_d1 <= rd_en;
|
rd_en_d1 <= rd_en;
|
eoi_wr_d1 <= eoi_wr;
|
eoi_wr_d1 <= eoi_wr;
|
|
|
-- defaults: encoded data write
|
-- defaults: encoded data write
|
ram_wren <= rd_en_d1;
|
ram_wren <= rd_en_d1;
|
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
|
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
|
ram_byte <= hr_q;
|
ram_byte <= hr_q;
|
|
|
-- start JFIF
|
-- start JFIF
|
if start = '1' and eoi = '0' then
|
if start = '1' and eoi = '0' then
|
rd_cnt <= (others => '0');
|
rd_cnt <= (others => '0');
|
rd_en <= '1';
|
rd_en <= '1';
|
elsif start = '1' and eoi = '1' then
|
elsif start = '1' and eoi = '1' then
|
eoi_wr <= '1';
|
eoi_wr <= '1';
|
eoi_cnt <= (others => '0');
|
eoi_cnt <= (others => '0');
|
end if;
|
end if;
|
|
|
-- read JFIF Header
|
-- read JFIF Header
|
if rd_en = '1' then
|
if rd_en = '1' then
|
if rd_cnt = C_HDR_SIZE-1 then
|
if rd_cnt = C_HDR_SIZE-1 then
|
rd_en <= '0';
|
rd_en <= '0';
|
ready <= '1';
|
ready <= '1';
|
else
|
else
|
rd_cnt <= rd_cnt + 1;
|
rd_cnt <= rd_cnt + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- EOI MARKER write
|
-- EOI MARKER write
|
if eoi_wr = '1' then
|
if eoi_wr = '1' then
|
if eoi_cnt = 2 then
|
if eoi_cnt = 2 then
|
eoi_cnt <= (others => '0');
|
eoi_cnt <= (others => '0');
|
eoi_wr <= '0';
|
eoi_wr <= '0';
|
ready <= '1';
|
ready <= '1';
|
else
|
else
|
eoi_cnt <= eoi_cnt + 1;
|
eoi_cnt <= eoi_cnt + 1;
|
ram_wren <= '1';
|
ram_wren <= '1';
|
if eoi_cnt = 0 then
|
if eoi_cnt = 0 then
|
ram_byte <= C_EOI(15 downto 8);
|
ram_byte <= C_EOI(15 downto 8);
|
ram_wraddr <= num_enc_bytes;
|
ram_wraddr <= num_enc_bytes;
|
elsif eoi_cnt = 1 then
|
elsif eoi_cnt = 1 then
|
ram_byte <= C_EOI(7 downto 0);
|
ram_byte <= C_EOI(7 downto 0);
|
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
|
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
|
to_unsigned(1,ram_wraddr'length));
|
to_unsigned(1,ram_wraddr'length));
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture RTL;
|
end architecture RTL;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture: end
|
-- Architecture: end
|
|
|
