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--------------------------------------------------------------------------------
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-- --
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-- --
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-- V H D L F I L E --
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-- V H D L F I L E --
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-- COPYRIGHT (C) 2006-2009 --
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-- COPYRIGHT (C) 2006-2009 --
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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-- Title : DIVIDER --
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-- Title : DIVIDER --
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-- Design : DCT QUANTIZER --
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-- Design : DCT QUANTIZER --
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-- Author : Michal Krepa --
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-- Author : Michal Krepa --
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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-- File : QUANTIZER.VHD --
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-- File : QUANTIZER.VHD --
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-- Created : Sun Aug 27 2006 --
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-- Created : Sun Aug 27 2006 --
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.All;
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use IEEE.STD_LOGIC_1164.All;
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use IEEE.NUMERIC_STD.all;
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use IEEE.NUMERIC_STD.all;
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entity quantizer is
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entity quantizer is
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generic
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generic
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(
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(
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SIZE_C : INTEGER := 12;
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SIZE_C : INTEGER := 12;
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RAMQADDR_W : INTEGER := 7;
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RAMQADDR_W : INTEGER := 7;
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RAMQDATA_W : INTEGER := 8
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RAMQDATA_W : INTEGER := 8
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);
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);
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port
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port
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(
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(
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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divalid : in STD_LOGIC;
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divalid : in STD_LOGIC;
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qdata : in std_logic_vector(7 downto 0);
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qdata : in std_logic_vector(7 downto 0);
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qwaddr : in std_logic_vector(6 downto 0);
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qwaddr : in std_logic_vector(6 downto 0);
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qwren : in std_logic;
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qwren : in std_logic;
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cmp_idx : in unsigned(1 downto 0);
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cmp_idx : in unsigned(2 downto 0);
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do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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dovalid : out STD_LOGIC
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dovalid : out STD_LOGIC
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);
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);
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end quantizer;
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end quantizer;
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architecture rtl of quantizer is
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architecture rtl of quantizer is
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constant INTERN_PIPE_C : INTEGER := 3;
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constant INTERN_PIPE_C : INTEGER := 3;
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signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0);
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signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0);
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signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
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signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
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signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
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signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
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signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal round_s : STD_LOGIC;
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signal round_s : STD_LOGIC;
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signal di_d1 : std_logic_vector(SIZE_C-1 downto 0);
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signal di_d1 : std_logic_vector(SIZE_C-1 downto 0);
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signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0);
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signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0);
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signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
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signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
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signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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signal table_select : std_logic;
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signal table_select : std_logic;
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begin
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begin
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----------------------------
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----------------------------
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-- RAMQ
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-- RAMQ
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----------------------------
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----------------------------
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U_RAMQ : entity work.RAMZ
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U_RAMQ : entity work.RAMZ
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generic map
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generic map
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(
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(
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RAMADDR_W => RAMQADDR_W,
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RAMADDR_W => RAMQADDR_W,
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RAMDATA_W => RAMQDATA_W
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RAMDATA_W => RAMQDATA_W
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)
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)
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port map
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port map
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(
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(
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d => qdata,
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d => qdata,
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waddr => qwaddr,
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waddr => qwaddr,
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raddr => slv_romaddr_s,
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raddr => slv_romaddr_s,
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we => qwren,
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we => qwren,
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clk => CLK,
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clk => CLK,
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q => romdatao_s
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q => romdatao_s
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);
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);
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divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;
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divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;
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divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
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divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
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r_divider : entity work.r_divider
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r_divider : entity work.r_divider
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port map
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port map
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(
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(
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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a => di_d1,
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a => di_d1,
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d => romdatao_s,
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d => romdatao_s,
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q => do_s
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q => do_s
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) ;
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) ;
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do <= do_s;
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do <= do_s;
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slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
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slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
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------------------------------
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------------------------------
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-- Quantization sub table select
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-- Quantization sub table select
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------------------------------
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------------------------------
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process(clk)
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process(clk)
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begin
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begin
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if clk = '1' and clk'event then
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if clk = '1' and clk'event then
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if rst = '1' then
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if rst = '1' then
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table_select <= '0';
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table_select <= '0';
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else
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else
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-- luminance table select
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-- luminance table select
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if cmp_idx = 0 then
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if cmp_idx < 2 then
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table_select <= '0';
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table_select <= '0';
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-- chrominance table select
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-- chrominance table select
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else
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else
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table_select <= '1';
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table_select <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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----------------------------
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----------------------------
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-- address incrementer
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-- address incrementer
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----------------------------
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----------------------------
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process(clk)
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process(clk)
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begin
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begin
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if clk = '1' and clk'event then
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if clk = '1' and clk'event then
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if rst = '1' then
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if rst = '1' then
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romaddr_s <= (others => '0');
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romaddr_s <= (others => '0');
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pipeline_reg <= (OTHERS => '0');
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pipeline_reg <= (OTHERS => '0');
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di_d1 <= (OTHERS => '0');
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di_d1 <= (OTHERS => '0');
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sign_bit_pipe <= (others => '0');
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sign_bit_pipe <= (others => '0');
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else
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else
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if divalid = '1' then
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if divalid = '1' then
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romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
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romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
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end if;
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end if;
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pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
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pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
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di_d1 <= di;
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di_d1 <= di;
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sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);
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sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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dovalid <= pipeline_reg(pipeline_reg'high);
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dovalid <= pipeline_reg(pipeline_reg'high);
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end rtl;
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end rtl;
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