--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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-- V H D L F I L E --
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-- V H D L F I L E --
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-- COPYRIGHT (C) 2009 --
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-- COPYRIGHT (C) 2009 --
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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-- Title : RLE --
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-- Title : RLE --
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-- Design : MDCT CORE --
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-- Design : MDCT CORE --
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-- Author : Michal Krepa --
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-- Author : Michal Krepa --
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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-- File : RLE.VHD --
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-- File : RLE.VHD --
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-- Created : Wed Mar 04 2009 --
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-- Created : Wed Mar 04 2009 --
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-- --
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-- --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- --
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-- --
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-- Description : Run Length Encoder --
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-- Description : Run Length Encoder --
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-- Baseline Entropy Coding --
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-- Baseline Entropy Coding --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.All;
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use IEEE.STD_LOGIC_1164.All;
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use IEEE.NUMERIC_STD.all;
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use IEEE.NUMERIC_STD.all;
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|
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library work;
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library work;
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use work.JPEG_PKG.all;
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use work.JPEG_PKG.all;
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|
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entity rle is
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entity rle is
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generic
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generic
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(
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(
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RAMADDR_W : INTEGER := 6;
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RAMADDR_W : INTEGER := 6;
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RAMDATA_W : INTEGER := 12
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RAMDATA_W : INTEGER := 12
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);
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);
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port
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port
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(
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(
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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start_pb : in std_logic;
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start_pb : in std_logic;
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sof : in std_logic;
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sof : in std_logic;
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rle_sm_settings : in T_SM_SETTINGS;
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rle_sm_settings : in T_SM_SETTINGS;
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|
|
runlength : out STD_LOGIC_VECTOR(3 downto 0);
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runlength : out STD_LOGIC_VECTOR(3 downto 0);
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size : out STD_LOGIC_VECTOR(3 downto 0);
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size : out STD_LOGIC_VECTOR(3 downto 0);
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amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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dovalid : out STD_LOGIC;
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dovalid : out STD_LOGIC;
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rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
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rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
|
);
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);
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end rle;
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end rle;
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|
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architecture rtl of rle is
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architecture rtl of rle is
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|
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|
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constant SIZE_REG_C : INTEGER := 4;
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constant SIZE_REG_C : INTEGER := 4;
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constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
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constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
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|
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signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);
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signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);
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signal acc_reg : SIGNED(RAMDATA_W downto 0);
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signal acc_reg : SIGNED(RAMDATA_W downto 0);
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signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
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signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
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signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
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signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
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signal runlength_reg : UNSIGNED(3 downto 0);
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signal runlength_reg : UNSIGNED(3 downto 0);
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signal dovalid_reg : STD_LOGIC;
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signal dovalid_reg : STD_LOGIC;
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signal zero_cnt : unsigned(5 downto 0);
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signal zero_cnt : unsigned(5 downto 0);
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signal wr_cnt_d1 : unsigned(5 downto 0);
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signal wr_cnt_d1 : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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|
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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|
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signal divalid : STD_LOGIC;
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signal divalid : STD_LOGIC;
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|
signal divalid_en : std_logic;
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signal zrl_proc : std_logic;
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signal zrl_proc : std_logic;
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signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
begin
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begin
|
|
|
size <= STD_LOGIC_VECTOR(size_reg);
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size <= STD_LOGIC_VECTOR(size_reg);
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amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
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amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
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|
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rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
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rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
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|
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-------------------------------------------
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-------------------------------------------
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-- MAIN PROCESSING
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-- MAIN PROCESSING
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-------------------------------------------
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-------------------------------------------
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process(clk,rst)
|
process(clk,rst)
|
begin
|
begin
|
if rst = '1' then
|
if rst = '1' then
|
wr_cnt_d1 <= (others => '0');
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wr_cnt_d1 <= (others => '0');
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prev_dc_reg_0 <= (others => '0');
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prev_dc_reg_0 <= (others => '0');
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prev_dc_reg_1 <= (others => '0');
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prev_dc_reg_1 <= (others => '0');
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prev_dc_reg_2 <= (others => '0');
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prev_dc_reg_2 <= (others => '0');
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dovalid_reg <= '0';
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dovalid_reg <= '0';
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acc_reg <= (others => '0');
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acc_reg <= (others => '0');
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runlength_reg <= (others => '0');
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runlength_reg <= (others => '0');
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runlength <= (others => '0');
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runlength <= (others => '0');
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dovalid <= '0';
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dovalid <= '0';
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zero_cnt <= (others => '0');
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zero_cnt <= (others => '0');
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zrl_proc <= '0';
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zrl_proc <= '0';
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rd_en <= '0';
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rd_en <= '0';
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rd_cnt <= (others => '0');
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rd_cnt <= (others => '0');
|
|
divalid_en <= '0';
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elsif clk = '1' and clk'event then
|
elsif clk = '1' and clk'event then
|
dovalid_reg <= '0';
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dovalid_reg <= '0';
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runlength_reg <= (others => '0');
|
runlength_reg <= (others => '0');
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wr_cnt_d1 <= wr_cnt;
|
wr_cnt_d1 <= wr_cnt;
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runlength <= std_logic_vector(runlength_reg);
|
runlength <= std_logic_vector(runlength_reg);
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dovalid <= dovalid_reg;
|
dovalid <= dovalid_reg;
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divalid <= rd_en;
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divalid <= rd_en;
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|
|
if start_pb = '1' then
|
if start_pb = '1' then
|
rd_cnt <= (others => '0');
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rd_cnt <= (others => '0');
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rd_en <= '1';
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rd_en <= '1';
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divalid_en <= '1';
|
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end if;
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|
|
|
if divalid = '1' and wr_cnt = 63 then
|
|
divalid_en <= '0';
|
end if;
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end if;
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|
|
-- input read enable
|
-- input read enable
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if rd_en = '1' then
|
if rd_en = '1' then
|
if rd_cnt = 64-1 then
|
if rd_cnt = 64-1 then
|
rd_cnt <= (others => '0');
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rd_cnt <= (others => '0');
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rd_en <= '0';
|
rd_en <= '0';
|
else
|
else
|
rd_cnt <= rd_cnt + 1;
|
rd_cnt <= rd_cnt + 1;
|
end if;
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end if;
|
end if;
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end if;
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|
|
-- input data valid
|
-- input data valid
|
if divalid = '1' then
|
if divalid = '1' then
|
wr_cnt <= wr_cnt + 1;
|
wr_cnt <= wr_cnt + 1;
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|
|
-- first DCT coefficient received, DC data
|
-- first DCT coefficient received, DC data
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if wr_cnt = 0 then
|
if wr_cnt = 0 then
|
-- differental coding of DC data per component
|
-- differental coding of DC data per component
|
case rle_sm_settings.cmp_idx is
|
case rle_sm_settings.cmp_idx is
|
when "00" =>
|
when "00" =>
|
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
|
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
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prev_dc_reg_0 <= SIGNED(di);
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prev_dc_reg_0 <= SIGNED(di);
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when "01" =>
|
when "01" =>
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
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prev_dc_reg_1 <= SIGNED(di);
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prev_dc_reg_1 <= SIGNED(di);
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when "10" =>
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when "10" =>
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
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prev_dc_reg_2 <= SIGNED(di);
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prev_dc_reg_2 <= SIGNED(di);
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when others =>
|
when others =>
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null;
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null;
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end case;
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end case;
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runlength_reg <= (others => '0');
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runlength_reg <= (others => '0');
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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-- AC coefficient
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-- AC coefficient
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else
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else
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-- zero AC
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-- zero AC
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if signed(di) = 0 then
|
if signed(di) = 0 then
|
-- EOB
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-- EOB
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if wr_cnt = 63 then
|
if wr_cnt = 63 then
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acc_reg <= (others => '0');
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acc_reg <= (others => '0');
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runlength_reg <= (others => '0');
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runlength_reg <= (others => '0');
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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-- no EOB
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-- no EOB
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else
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else
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zero_cnt <= zero_cnt + 1;
|
zero_cnt <= zero_cnt + 1;
|
end if;
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end if;
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-- non-zero AC
|
-- non-zero AC
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else
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else
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-- normal RLE case
|
-- normal RLE case
|
if zero_cnt <= 15 then
|
if zero_cnt <= 15 then
|
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
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acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
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runlength_reg <= zero_cnt(3 downto 0);
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runlength_reg <= zero_cnt(3 downto 0);
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zero_cnt <= (others => '0');
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zero_cnt <= (others => '0');
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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-- zero_cnt > 15
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-- zero_cnt > 15
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else
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else
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-- generate ZRL
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-- generate ZRL
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acc_reg <= (others => '0');
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acc_reg <= (others => '0');
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runlength_reg <= X"F";
|
runlength_reg <= X"F";
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zero_cnt <= zero_cnt - 16;
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zero_cnt <= zero_cnt - 16;
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dovalid_reg <= '1';
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dovalid_reg <= '1';
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-- stall input until ZRL is handled
|
-- stall input until ZRL is handled
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zrl_proc <= '1';
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zrl_proc <= '1';
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zrl_di <= di;
|
zrl_di <= di;
|
divalid <= '0';
|
divalid <= '0';
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rd_cnt <= rd_cnt;
|
rd_cnt <= rd_cnt;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- ZRL processing
|
-- ZRL processing
|
if zrl_proc = '1' then
|
if zrl_proc = '1' then
|
if zero_cnt <= 15 then
|
if zero_cnt <= 15 then
|
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
|
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
|
runlength_reg <= zero_cnt(3 downto 0);
|
runlength_reg <= zero_cnt(3 downto 0);
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if signed(zrl_di) = 0 then
|
if signed(zrl_di) = 0 then
|
zero_cnt <= to_unsigned(1,zero_cnt'length);
|
zero_cnt <= to_unsigned(1,zero_cnt'length);
|
else
|
else
|
zero_cnt <= (others => '0');
|
zero_cnt <= (others => '0');
|
end if;
|
end if;
|
dovalid_reg <= '1';
|
dovalid_reg <= '1';
|
divalid <= '1';
|
divalid <= divalid_en;
|
-- continue input handling
|
-- continue input handling
|
zrl_proc <= '0';
|
zrl_proc <= '0';
|
-- zero_cnt > 15
|
-- zero_cnt > 15
|
else
|
else
|
-- generate ZRL
|
-- generate ZRL
|
acc_reg <= (others => '0');
|
acc_reg <= (others => '0');
|
runlength_reg <= X"F";
|
runlength_reg <= X"F";
|
zero_cnt <= zero_cnt - 16;
|
zero_cnt <= zero_cnt - 16;
|
dovalid_reg <= '1';
|
dovalid_reg <= '1';
|
divalid <= '0';
|
divalid <= '0';
|
rd_cnt <= rd_cnt;
|
rd_cnt <= rd_cnt;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- start of 8x8 block processing
|
-- start of 8x8 block processing
|
if start_pb = '1' then
|
if start_pb = '1' then
|
zero_cnt <= (others => '0');
|
zero_cnt <= (others => '0');
|
wr_cnt <= (others => '0');
|
wr_cnt <= (others => '0');
|
end if;
|
end if;
|
|
|
if sof = '1' then
|
if sof = '1' then
|
prev_dc_reg_0 <= (others => '0');
|
prev_dc_reg_0 <= (others => '0');
|
prev_dc_reg_1 <= (others => '0');
|
prev_dc_reg_1 <= (others => '0');
|
prev_dc_reg_2 <= (others => '0');
|
prev_dc_reg_2 <= (others => '0');
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- Entropy Coder
|
-- Entropy Coder
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
p_entropy_coder : process(CLK, RST)
|
p_entropy_coder : process(CLK, RST)
|
begin
|
begin
|
if RST = '1' then
|
if RST = '1' then
|
ampli_vli_reg <= (others => '0');
|
ampli_vli_reg <= (others => '0');
|
size_reg <= (others => '0');
|
size_reg <= (others => '0');
|
elsif CLK'event and CLK = '1' then
|
elsif CLK'event and CLK = '1' then
|
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
|
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
|
-- positive input
|
-- positive input
|
if acc_reg >= 0 then
|
if acc_reg >= 0 then
|
ampli_vli_reg <= acc_reg;
|
ampli_vli_reg <= acc_reg;
|
else
|
else
|
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
|
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
|
end if;
|
end if;
|
|
|
-- compute Symbol-1 Size
|
-- compute Symbol-1 Size
|
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
|
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
|
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
|
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
|
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
|
end if;
|
end if;
|
|
|
-- compute Symbol-1 Size
|
-- compute Symbol-1 Size
|
-- positive input
|
-- positive input
|
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
|
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
|
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
|
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
|
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
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elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
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size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
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elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
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elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
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size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
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size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
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elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
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elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
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size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
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elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
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size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
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elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
|
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
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elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
|
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
|
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
|
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
|
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
|
end if;
|
end if;
|
|
|
-- DC coefficient amplitude=0 case OR EOB
|
-- DC coefficient amplitude=0 case OR EOB
|
if acc_reg = 0 then
|
if acc_reg = 0 then
|
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
|
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end rtl;
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end rtl;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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