-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File Name : RleDoubleFifo.vhd
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-- File Name : RleDoubleFifo.vhd
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--
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--
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-- Project : JPEG_ENC
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-- Project : JPEG_ENC
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--
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--
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-- Module : RleDoubleFifo
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-- Module : RleDoubleFifo
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--
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--
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-- Content : RleDoubleFifo
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-- Content : RleDoubleFifo
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--
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--
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-- Description :
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-- Description :
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--
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--
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-- Spec. :
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-- Spec. :
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--
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--
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-- Author : Michal Krepa
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-- Author : Michal Krepa
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- History :
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-- History :
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-- 20090228: (MK): Initial Creation.
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-- 20090228: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity RleDoubleFifo is
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entity RleDoubleFifo is
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port
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port
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(
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(
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CLK : in std_logic;
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CLK : in std_logic;
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RST : in std_logic;
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RST : in std_logic;
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-- HUFFMAN
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-- HUFFMAN
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data_in : in std_logic_vector(19 downto 0);
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data_in : in std_logic_vector(19 downto 0);
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wren : in std_logic;
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wren : in std_logic;
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-- BYTE STUFFER
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-- BYTE STUFFER
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buf_sel : in std_logic;
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buf_sel : in std_logic;
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rd_req : in std_logic;
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rd_req : in std_logic;
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fifo_empty : out std_logic;
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fifo_empty : out std_logic;
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data_out : out std_logic_vector(19 downto 0)
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data_out : out std_logic_vector(19 downto 0)
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);
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);
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end entity RleDoubleFifo;
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end entity RleDoubleFifo;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of RleDoubleFifo is
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architecture RTL of RleDoubleFifo is
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|
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signal fifo1_rd : std_logic;
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signal fifo1_rd : std_logic;
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signal fifo1_wr : std_logic;
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signal fifo1_wr : std_logic;
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signal fifo1_q : std_logic_vector(19 downto 0);
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signal fifo1_q : std_logic_vector(19 downto 0);
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signal fifo1_full : std_logic;
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signal fifo1_full : std_logic;
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signal fifo1_empty : std_logic;
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signal fifo1_empty : std_logic;
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signal fifo1_count : std_logic_vector(6 downto 0);
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signal fifo1_count : std_logic_vector(6 downto 0);
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|
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signal fifo2_rd : std_logic;
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signal fifo2_rd : std_logic;
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signal fifo2_wr : std_logic;
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signal fifo2_wr : std_logic;
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signal fifo2_q : std_logic_vector(19 downto 0);
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signal fifo2_q : std_logic_vector(19 downto 0);
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signal fifo2_full : std_logic;
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signal fifo2_full : std_logic;
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signal fifo2_empty : std_logic;
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signal fifo2_empty : std_logic;
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signal fifo2_count : std_logic_vector(6 downto 0);
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signal fifo2_count : std_logic_vector(6 downto 0);
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|
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signal fifo_data_in : std_logic_vector(19 downto 0);
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signal fifo_data_in : std_logic_vector(19 downto 0);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- FIFO 1
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-- FIFO 1
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_FIFO_1 : entity work.FIFO
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U_FIFO_1 : entity work.FIFO
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generic map
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generic map
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(
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(
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DATA_WIDTH => 20,
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DATA_WIDTH => 20,
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ADDR_WIDTH => 6
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ADDR_WIDTH => 6
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)
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)
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port map
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port map
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(
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(
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rst => RST,
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rst => RST,
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clk => CLK,
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clk => CLK,
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rinc => fifo1_rd,
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rinc => fifo1_rd,
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winc => fifo1_wr,
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winc => fifo1_wr,
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datai => fifo_data_in,
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datai => fifo_data_in,
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|
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datao => fifo1_q,
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datao => fifo1_q,
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fullo => fifo1_full,
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fullo => fifo1_full,
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emptyo => fifo1_empty,
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emptyo => fifo1_empty,
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count => fifo1_count
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count => fifo1_count
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);
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);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- FIFO 2
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-- FIFO 2
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_FIFO_2 : entity work.FIFO
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U_FIFO_2 : entity work.FIFO
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generic map
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generic map
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(
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(
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DATA_WIDTH => 20,
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DATA_WIDTH => 20,
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ADDR_WIDTH => 6
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ADDR_WIDTH => 6
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)
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)
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port map
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port map
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(
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(
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rst => RST,
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rst => RST,
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clk => CLK,
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clk => CLK,
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rinc => fifo2_rd,
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rinc => fifo2_rd,
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winc => fifo2_wr,
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winc => fifo2_wr,
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datai => fifo_data_in,
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datai => fifo_data_in,
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|
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datao => fifo2_q,
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datao => fifo2_q,
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fullo => fifo2_full,
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fullo => fifo2_full,
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emptyo => fifo2_empty,
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emptyo => fifo2_empty,
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count => fifo2_count
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count => fifo2_count
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);
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);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- mux2
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-- mux2
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_mux2 : process(CLK, RST)
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p_mux2 : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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fifo1_wr <= '0';
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fifo1_wr <= '0';
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fifo2_wr <= '0';
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fifo2_wr <= '0';
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fifo_data_in <= (others => '0');
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fifo_data_in <= (others => '0');
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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if buf_sel = '0' then
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if buf_sel = '0' then
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fifo1_wr <= wren;
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fifo1_wr <= wren;
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else
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else
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fifo2_wr <= wren;
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fifo2_wr <= wren;
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end if;
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end if;
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fifo_data_in <= data_in;
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fifo_data_in <= data_in;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- mux3
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-- mux3
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_mux3 : process(CLK, RST)
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p_mux3 : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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data_out <= (others => '0');
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--data_out <= (others => '0');
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fifo1_rd <= '0';
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--fifo1_rd <= '0';
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fifo2_rd <= '0';
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--fifo2_rd <= '0';
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fifo_empty <= '0';
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--fifo_empty <= '0';
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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if buf_sel = '1' then
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if buf_sel = '1' then
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data_out <= fifo1_q;
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--data_out <= fifo1_q;
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fifo1_rd <= rd_req;
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--fifo1_rd <= rd_req;
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fifo_empty <= fifo1_empty;
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--fifo_empty <= fifo1_empty;
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else
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else
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data_out <= fifo2_q;
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--data_out <= fifo2_q;
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fifo2_rd <= rd_req;
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--fifo2_rd <= rd_req;
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fifo_empty <= fifo2_empty;
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--fifo_empty <= fifo2_empty;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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fifo1_rd <= rd_req when buf_sel = '1' else '0';
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fifo2_rd <= rd_req when buf_sel = '0' else '0';
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data_out <= fifo1_q when buf_sel = '1' else fifo2_q;
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fifo_empty <= fifo1_empty when buf_sel = '1' else fifo2_empty;
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end architecture RTL;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: end
|
-- Architecture: end
|
|
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