-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File Name : ZZ_TOP.vhd
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-- File Name : ZZ_TOP.vhd
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--
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--
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-- Project : JPEG_ENC
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-- Project : JPEG_ENC
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--
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--
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-- Module : ZZ_TOP
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-- Module : ZZ_TOP
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--
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--
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-- Content : ZigZag Top level
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-- Content : ZigZag Top level
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--
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--
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-- Description : Zig Zag scan and Quantizer
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-- Description : Zig Zag scan
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--
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--
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-- Spec. :
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-- Spec. :
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--
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--
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-- Author : Michal Krepa
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-- Author : Michal Krepa
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- History :
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-- History :
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-- 20090301: (MK): Initial Creation.
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-- 20090301: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library work;
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library work;
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use work.JPEG_PKG.all;
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use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity ZZ_TOP is
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entity ZZ_TOP is
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port
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port
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(
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(
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CLK : in std_logic;
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CLK : in std_logic;
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RST : in std_logic;
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RST : in std_logic;
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-- CTRL
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-- CTRL
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start_pb : in std_logic;
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start_pb : in std_logic;
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ready_pb : out std_logic;
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ready_pb : out std_logic;
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zig_sm_settings : in T_SM_SETTINGS;
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zig_sm_settings : in T_SM_SETTINGS;
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|
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-- RLE
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-- Quantizer
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rle_buf_sel : in std_logic;
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qua_buf_sel : in std_logic;
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rle_rdaddr : in std_logic_vector(5 downto 0);
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qua_rdaddr : in std_logic_vector(5 downto 0);
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rle_data : out std_logic_vector(11 downto 0);
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qua_data : out std_logic_vector(11 downto 0);
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|
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-- FDCT
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-- FDCT
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fdct_buf_sel : out std_logic;
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fdct_buf_sel : out std_logic;
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fdct_rd_addr : out std_logic_vector(5 downto 0);
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fdct_rd_addr : out std_logic_vector(5 downto 0);
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fdct_data : in std_logic_vector(11 downto 0);
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fdct_data : in std_logic_vector(11 downto 0);
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fdct_rden : out std_logic;
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fdct_rden : out std_logic
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|
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-- HOST
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qdata : in std_logic_vector(7 downto 0);
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qaddr : in std_logic_vector(6 downto 0);
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qwren : in std_logic
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);
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);
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end entity ZZ_TOP;
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end entity ZZ_TOP;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of ZZ_TOP is
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architecture RTL of ZZ_TOP is
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|
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signal dbuf_data : std_logic_vector(11 downto 0);
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signal dbuf_data : std_logic_vector(11 downto 0);
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signal dbuf_q : std_logic_vector(11 downto 0);
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signal dbuf_q : std_logic_vector(11 downto 0);
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signal dbuf_we : std_logic;
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signal dbuf_we : std_logic;
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signal dbuf_waddr : std_logic_vector(6 downto 0);
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signal dbuf_waddr : std_logic_vector(6 downto 0);
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signal dbuf_raddr : std_logic_vector(6 downto 0);
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signal dbuf_raddr : std_logic_vector(6 downto 0);
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signal zigzag_di : std_logic_vector(11 downto 0);
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signal zigzag_di : std_logic_vector(11 downto 0);
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signal zigzag_divalid : std_logic;
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signal zigzag_divalid : std_logic;
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signal zigzag_dout : std_logic_vector(11 downto 0);
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signal zigzag_dout : std_logic_vector(11 downto 0);
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signal zigzag_dovalid : std_logic;
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signal zigzag_dovalid : std_logic;
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signal quant_dout : std_logic_vector(11 downto 0);
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signal quant_dovalid : std_logic;
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signal wr_cnt : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_en_d : std_logic_vector(5 downto 0);
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signal rd_en_d : std_logic_vector(5 downto 0);
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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signal fdct_buf_sel_s : std_logic;
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signal fdct_buf_sel_s : std_logic;
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signal zz_rd_addr : std_logic_vector(5 downto 0);
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signal zz_rd_addr : std_logic_vector(5 downto 0);
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signal fifo_empty : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_rden : std_logic;
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signal fifo_rden : std_logic;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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|
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fdct_rd_addr <= std_logic_vector(zz_rd_addr);
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fdct_rd_addr <= std_logic_vector(zz_rd_addr);
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rle_data <= dbuf_q;
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qua_data <= dbuf_q;
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fdct_buf_sel <= fdct_buf_sel_s;
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fdct_buf_sel <= fdct_buf_sel_s;
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fdct_rden <= rd_en;
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fdct_rden <= rd_en;
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|
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- ZigZag Core
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-- ZigZag Core
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_zigzag : entity work.zigzag
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U_zigzag : entity work.zigzag
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generic map
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generic map
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(
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(
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RAMADDR_W => 6,
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RAMADDR_W => 6,
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RAMDATA_W => 12
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RAMDATA_W => 12
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)
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)
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port map
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port map
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(
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(
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rst => RST,
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rst => RST,
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clk => CLK,
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clk => CLK,
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di => zigzag_di,
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di => zigzag_di,
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divalid => zigzag_divalid,
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divalid => zigzag_divalid,
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rd_addr => rd_cnt,
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rd_addr => rd_cnt,
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fifo_rden => fifo_rden,
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fifo_rden => fifo_rden,
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|
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fifo_empty => fifo_empty,
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fifo_empty => fifo_empty,
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dout => zigzag_dout,
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dout => zigzag_dout,
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dovalid => zigzag_dovalid,
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dovalid => zigzag_dovalid,
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zz_rd_addr => zz_rd_addr
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zz_rd_addr => zz_rd_addr
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);
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);
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|
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zigzag_di <= fdct_data;
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zigzag_di <= fdct_data;
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zigzag_divalid <= rd_en_d(1);
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zigzag_divalid <= rd_en_d(1);
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|
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Quantizer
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-------------------------------------------------------------------
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U_quantizer : entity work.quantizer
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generic map
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(
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SIZE_C => 12,
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RAMQADDR_W => 7,
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RAMQDATA_W => 8
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)
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port map
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(
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rst => RST,
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clk => CLK,
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di => zigzag_dout,
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divalid => zigzag_dovalid,
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qdata => qdata,
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qwaddr => qaddr,
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qwren => qwren,
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cmp_idx => zig_sm_settings.cmp_idx,
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|
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do => quant_dout,
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dovalid => quant_dovalid
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);
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-------------------------------------------------------------------
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-- DBUF
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-- DBUF
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_RAMZ : entity work.RAMZ
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U_RAMZ : entity work.RAMZ
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generic map
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generic map
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(
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(
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RAMADDR_W => 7,
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RAMADDR_W => 7,
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RAMDATA_W => 12
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RAMDATA_W => 12
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)
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)
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port map
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port map
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(
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(
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d => dbuf_data,
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d => dbuf_data,
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waddr => dbuf_waddr,
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waddr => dbuf_waddr,
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raddr => dbuf_raddr,
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raddr => dbuf_raddr,
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we => dbuf_we,
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we => dbuf_we,
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clk => CLK,
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clk => CLK,
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|
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q => dbuf_q
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q => dbuf_q
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);
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);
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|
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dbuf_data <= quant_dout;
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dbuf_data <= zigzag_dout;
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dbuf_waddr <= (not rle_buf_sel) & std_logic_vector(wr_cnt);
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dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
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dbuf_we <= quant_dovalid;
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dbuf_we <= zigzag_dovalid;
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dbuf_raddr <= rle_buf_sel & rle_rdaddr;
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dbuf_raddr <= qua_buf_sel & qua_rdaddr;
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|
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- FIFO Ctrl
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-- FIFO Ctrl
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_fifo_ctrl : process(CLK, RST)
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p_fifo_ctrl : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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fifo_rden <= '0';
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fifo_rden <= '0';
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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if fifo_empty = '0' then
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if fifo_empty = '0' then
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fifo_rden <= '1';
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fifo_rden <= '1';
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else
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else
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fifo_rden <= '0';
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fifo_rden <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Counter1
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-- Counter1
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_counter1 : process(CLK, RST)
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p_counter1 : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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rd_en <= '0';
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rd_en <= '0';
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rd_en_d <= (others => '0');
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rd_en_d <= (others => '0');
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rd_cnt <= (others => '0');
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rd_cnt <= (others => '0');
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
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rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
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|
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if start_pb = '1' then
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if start_pb = '1' then
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rd_cnt <= (others => '0');
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rd_cnt <= (others => '0');
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rd_en <= '1';
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rd_en <= '1';
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end if;
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end if;
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|
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if rd_en = '1' then
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if rd_en = '1' then
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if rd_cnt = 64-1 then
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if rd_cnt = 64-1 then
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rd_cnt <= (others => '0');
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rd_cnt <= (others => '0');
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rd_en <= '0';
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rd_en <= '0';
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else
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else
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rd_cnt <= rd_cnt + 1;
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rd_cnt <= rd_cnt + 1;
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end if;
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end if;
|
end if;
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end if;
|
|
|
end if;
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end if;
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end process;
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end process;
|
|
|
-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- wr_cnt
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-- wr_cnt
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_wr_cnt : process(CLK, RST)
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p_wr_cnt : process(CLK, RST)
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begin
|
begin
|
if RST = '1' then
|
if RST = '1' then
|
wr_cnt <= (others => '0');
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wr_cnt <= (others => '0');
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ready_pb <= '0';
|
ready_pb <= '0';
|
elsif CLK'event and CLK = '1' then
|
elsif CLK'event and CLK = '1' then
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ready_pb <= '0';
|
ready_pb <= '0';
|
|
|
if start_pb = '1' then
|
if start_pb = '1' then
|
wr_cnt <= (others => '0');
|
wr_cnt <= (others => '0');
|
end if;
|
end if;
|
|
|
if quant_dovalid = '1' then
|
if zigzag_dovalid = '1' then
|
if wr_cnt = 64-1 then
|
if wr_cnt = 64-1 then
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wr_cnt <= (others => '0');
|
wr_cnt <= (others => '0');
|
ready_pb <= '1';
|
|
else
|
else
|
wr_cnt <=wr_cnt + 1;
|
wr_cnt <=wr_cnt + 1;
|
end if;
|
end if;
|
|
|
|
-- give ready ahead to save cycles!
|
|
if wr_cnt = 64-1-3 then
|
|
ready_pb <= '1';
|
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- fdct_buf_sel
|
-- fdct_buf_sel
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
p_buf_sel : process(CLK, RST)
|
p_buf_sel : process(CLK, RST)
|
begin
|
begin
|
if RST = '1' then
|
if RST = '1' then
|
fdct_buf_sel_s <= '0';
|
fdct_buf_sel_s <= '0';
|
elsif CLK'event and CLK = '1' then
|
elsif CLK'event and CLK = '1' then
|
if start_pb = '1' then
|
if start_pb = '1' then
|
fdct_buf_sel_s <= not fdct_buf_sel_s;
|
fdct_buf_sel_s <= not fdct_buf_sel_s;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end architecture RTL;
|
end architecture RTL;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture: end
|
-- Architecture: end
|
|
|
