---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- TITLE: Memory Controller
|
-- TITLE: Memory Controller
|
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
|
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
|
-- DATE CREATED: 1/31/01
|
-- DATE CREATED: 1/31/01
|
-- FILENAME: mem_ctrl.vhd
|
-- FILENAME: mem_ctrl.vhd
|
-- PROJECT: Plasma CPU core
|
-- PROJECT: Plasma CPU core
|
-- COPYRIGHT: Software placed into the public domain by the author.
|
-- COPYRIGHT: Software placed into the public domain by the author.
|
-- Software 'as is' without warranty. Author liable for nothing.
|
-- Software 'as is' without warranty. Author liable for nothing.
|
-- DESCRIPTION:
|
-- DESCRIPTION:
|
-- Memory controller for the Plasma CPU.
|
-- Memory controller for the Plasma CPU.
|
-- Supports Big or Little Endian mode.
|
-- Supports Big or Little Endian mode.
|
-- Four cycles for a write unless a(31)='1' then two cycles.
|
-- Four cycles for a write unless a(31)='1' then two cycles.
|
-- This entity could implement interfaces to:
|
-- This entity could implement interfaces to:
|
-- Data cache
|
-- Data cache
|
-- Address cache
|
-- Address cache
|
-- Memory management unit (MMU)
|
-- Memory management unit (MMU)
|
-- DRAM controller
|
-- DRAM controller
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use work.mlite_pack.all;
|
use work.mlite_pack.all;
|
|
|
entity mem_ctrl is
|
entity mem_ctrl is
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pause_in : in std_logic;
|
pause_in : in std_logic;
|
nullify_op : in std_logic;
|
nullify_op : in std_logic;
|
address_pc : in std_logic_vector(31 downto 0);
|
address_pc : in std_logic_vector(31 downto 0);
|
opcode_out : out std_logic_vector(31 downto 0);
|
opcode_out : out std_logic_vector(31 downto 0);
|
|
|
address_data : in std_logic_vector(31 downto 0);
|
address_data : in std_logic_vector(31 downto 0);
|
mem_source : in mem_source_type;
|
mem_source : in mem_source_type;
|
data_write : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic;
|
pause_out : out std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_byte_sel : out std_logic_vector(3 downto 0);
|
mem_byte_sel : out std_logic_vector(3 downto 0);
|
mem_write : out std_logic;
|
mem_write : out std_logic;
|
mem_pause : in std_logic);
|
mem_pause : in std_logic);
|
end; --entity mem_ctrl
|
end; --entity mem_ctrl
|
|
|
architecture logic of mem_ctrl is
|
architecture logic of mem_ctrl is
|
--"00" = big_endian; "11" = little_endian
|
--"00" = big_endian; "11" = little_endian
|
constant little_endian : std_logic_vector(1 downto 0) := "00";
|
constant little_endian : std_logic_vector(1 downto 0) := "00";
|
signal opcode_reg : std_logic_vector(31 downto 0);
|
signal opcode_reg : std_logic_vector(31 downto 0);
|
signal next_opcode_reg : std_logic_vector(31 downto 0);
|
signal next_opcode_reg : std_logic_vector(31 downto 0);
|
|
|
subtype setup_state_type is std_logic_vector(1 downto 0);
|
subtype setup_state_type is std_logic_vector(1 downto 0);
|
signal setup_state : setup_state_type;
|
signal setup_state : setup_state_type;
|
constant STATE_FETCH : setup_state_type := "00";
|
constant STATE_FETCH : setup_state_type := "00";
|
constant STATE_ADDR : setup_state_type := "01";
|
constant STATE_ADDR : setup_state_type := "01";
|
constant STATE_WRITE : setup_state_type := "10";
|
constant STATE_WRITE : setup_state_type := "10";
|
constant STATE_PAUSE : setup_state_type := "11";
|
constant STATE_PAUSE : setup_state_type := "11";
|
begin
|
begin
|
|
|
mem_proc: process(clk, reset_in, pause_in, nullify_op,
|
mem_proc: process(clk, reset_in, pause_in, nullify_op,
|
address_pc, address_data, mem_source, data_write,
|
address_pc, address_data, mem_source, data_write,
|
mem_data_r, mem_pause,
|
mem_data_r, mem_pause,
|
opcode_reg, next_opcode_reg, setup_state)
|
opcode_reg, next_opcode_reg, setup_state)
|
variable data, datab : std_logic_vector(31 downto 0);
|
variable data, datab : std_logic_vector(31 downto 0);
|
variable opcode_next : std_logic_vector(31 downto 0);
|
variable opcode_next : std_logic_vector(31 downto 0);
|
variable byte_sel_next : std_logic_vector(3 downto 0);
|
variable byte_sel_next : std_logic_vector(3 downto 0);
|
variable write_next : std_logic;
|
variable write_next : std_logic;
|
variable setup_state_next : setup_state_type;
|
variable setup_state_next : setup_state_type;
|
variable pause : std_logic;
|
variable pause : std_logic;
|
variable address_next : std_logic_vector(31 downto 0);
|
variable address_next : std_logic_vector(31 downto 0);
|
variable bits : std_logic_vector(1 downto 0);
|
variable bits : std_logic_vector(1 downto 0);
|
variable mem_data_w_v : std_logic_vector(31 downto 0);
|
variable mem_data_w_v : std_logic_vector(31 downto 0);
|
begin
|
begin
|
byte_sel_next := "0000";
|
byte_sel_next := "0000";
|
write_next := '0';
|
write_next := '0';
|
pause := '0';
|
pause := '0';
|
setup_state_next := setup_state;
|
setup_state_next := setup_state;
|
|
|
address_next := address_pc;
|
address_next := address_pc;
|
data := mem_data_r;
|
data := mem_data_r;
|
datab := ZERO;
|
datab := ZERO;
|
mem_data_w_v := ZERO;
|
mem_data_w_v := ZERO;
|
|
|
case mem_source is
|
case mem_source is
|
when mem_read32 =>
|
when mem_read32 =>
|
datab := data;
|
datab := data;
|
when mem_read16 | mem_read16s =>
|
when mem_read16 | mem_read16s =>
|
if address_data(1) = little_endian(1) then
|
if address_data(1) = little_endian(1) then
|
datab(15 downto 0) := data(31 downto 16);
|
datab(15 downto 0) := data(31 downto 16);
|
else
|
else
|
datab(15 downto 0) := data(15 downto 0);
|
datab(15 downto 0) := data(15 downto 0);
|
end if;
|
end if;
|
if mem_source = mem_read16 or datab(15) = '0' then
|
if mem_source = mem_read16 or datab(15) = '0' then
|
datab(31 downto 16) := ZERO(31 downto 16);
|
datab(31 downto 16) := ZERO(31 downto 16);
|
else
|
else
|
datab(31 downto 16) := ONES(31 downto 16);
|
datab(31 downto 16) := ONES(31 downto 16);
|
end if;
|
end if;
|
when mem_read8 | mem_read8s =>
|
when mem_read8 | mem_read8s =>
|
bits := address_data(1 downto 0) xor little_endian;
|
bits := address_data(1 downto 0) xor little_endian;
|
case bits is
|
case bits is
|
when "00" => datab(7 downto 0) := data(31 downto 24);
|
when "00" => datab(7 downto 0) := data(31 downto 24);
|
when "01" => datab(7 downto 0) := data(23 downto 16);
|
when "01" => datab(7 downto 0) := data(23 downto 16);
|
when "10" => datab(7 downto 0) := data(15 downto 8);
|
when "10" => datab(7 downto 0) := data(15 downto 8);
|
when others => datab(7 downto 0) := data(7 downto 0);
|
when others => datab(7 downto 0) := data(7 downto 0);
|
end case;
|
end case;
|
if mem_source = mem_read8 or datab(7) = '0' then
|
if mem_source = mem_read8 or datab(7) = '0' then
|
datab(31 downto 8) := ZERO(31 downto 8);
|
datab(31 downto 8) := ZERO(31 downto 8);
|
else
|
else
|
datab(31 downto 8) := ONES(31 downto 8);
|
datab(31 downto 8) := ONES(31 downto 8);
|
end if;
|
end if;
|
when mem_write32 =>
|
when mem_write32 =>
|
write_next := '1';
|
write_next := '1';
|
mem_data_w_v := data_write;
|
mem_data_w_v := data_write;
|
byte_sel_next := "1111";
|
byte_sel_next := "1111";
|
when mem_write16 =>
|
when mem_write16 =>
|
write_next := '1';
|
write_next := '1';
|
mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
|
mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
|
if address_data(1) = little_endian(1) then
|
if address_data(1) = little_endian(1) then
|
byte_sel_next := "1100";
|
byte_sel_next := "1100";
|
else
|
else
|
byte_sel_next := "0011";
|
byte_sel_next := "0011";
|
end if;
|
end if;
|
when mem_write8 =>
|
when mem_write8 =>
|
write_next := '1';
|
write_next := '1';
|
mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
|
mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
|
data_write(7 downto 0) & data_write(7 downto 0);
|
data_write(7 downto 0) & data_write(7 downto 0);
|
bits := address_data(1 downto 0) xor little_endian;
|
bits := address_data(1 downto 0) xor little_endian;
|
case bits is
|
case bits is
|
when "00" =>
|
when "00" =>
|
byte_sel_next := "1000";
|
byte_sel_next := "1000";
|
when "01" =>
|
when "01" =>
|
byte_sel_next := "0100";
|
byte_sel_next := "0100";
|
when "10" =>
|
when "10" =>
|
byte_sel_next := "0010";
|
byte_sel_next := "0010";
|
when others =>
|
when others =>
|
byte_sel_next := "0001";
|
byte_sel_next := "0001";
|
end case;
|
end case;
|
when others =>
|
when others =>
|
end case;
|
end case;
|
|
|
opcode_next := opcode_reg;
|
opcode_next := opcode_reg;
|
if mem_source = mem_none then
|
if mem_source = mem_none then
|
setup_state_next := STATE_FETCH;
|
setup_state_next := STATE_FETCH;
|
if pause_in = '0' and mem_pause = '0' then
|
if pause_in = '0' and mem_pause = '0' then
|
opcode_next := data;
|
opcode_next := data;
|
end if;
|
end if;
|
else
|
else
|
if setup_state = STATE_FETCH then
|
if setup_state = STATE_FETCH then
|
pause := '1';
|
pause := '1';
|
byte_sel_next := "0000";
|
byte_sel_next := "0000";
|
|
if mem_pause = '0' then
|
setup_state_next := STATE_ADDR;
|
setup_state_next := STATE_ADDR;
|
|
end if;
|
elsif setup_state = STATE_ADDR then
|
elsif setup_state = STATE_ADDR then
|
address_next := address_data;
|
address_next := address_data;
|
if write_next ='1' and address_data(31) = '0' then
|
if write_next ='1' and address_data(31) = '0' then
|
pause := '1';
|
pause := '1';
|
byte_sel_next := "0000";
|
byte_sel_next := "0000";
|
|
if mem_pause = '0' then
|
setup_state_next := STATE_WRITE; --4 cycle access
|
setup_state_next := STATE_WRITE; --4 cycle access
|
|
end if;
|
else
|
else
|
if mem_pause = '0' then
|
if mem_pause = '0' then
|
opcode_next := next_opcode_reg;
|
opcode_next := next_opcode_reg;
|
setup_state_next := STATE_FETCH; --2 cycle access
|
setup_state_next := STATE_FETCH; --2 cycle access
|
end if;
|
end if;
|
end if;
|
end if;
|
elsif setup_state = STATE_WRITE then
|
elsif setup_state = STATE_WRITE then
|
pause := '1';
|
pause := '1';
|
address_next := address_data;
|
address_next := address_data;
|
if mem_pause = '0' then
|
if mem_pause = '0' then
|
setup_state_next := STATE_PAUSE;
|
setup_state_next := STATE_PAUSE;
|
end if;
|
end if;
|
elsif setup_state = STATE_PAUSE then
|
elsif setup_state = STATE_PAUSE then
|
address_next := address_data;
|
address_next := address_data;
|
byte_sel_next := "0000";
|
byte_sel_next := "0000";
|
opcode_next := next_opcode_reg;
|
opcode_next := next_opcode_reg;
|
|
if mem_pause = '0' then
|
setup_state_next := STATE_FETCH;
|
setup_state_next := STATE_FETCH;
|
end if;
|
end if;
|
|
end if;
|
end if;
|
end if;
|
|
|
if nullify_op = '1' then
|
if nullify_op = '1' then
|
opcode_next := ZERO; --NOP
|
opcode_next := ZERO; --NOP
|
end if;
|
end if;
|
if reset_in = '1' then
|
if reset_in = '1' then
|
setup_state_next := STATE_FETCH;
|
setup_state_next := STATE_FETCH;
|
opcode_next := ZERO;
|
opcode_next := ZERO;
|
end if;
|
end if;
|
|
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
opcode_reg <= opcode_next;
|
opcode_reg <= opcode_next;
|
if setup_state = STATE_FETCH then
|
if setup_state = STATE_FETCH then
|
next_opcode_reg <= data;
|
next_opcode_reg <= data;
|
end if;
|
end if;
|
setup_state <= setup_state_next;
|
setup_state <= setup_state_next;
|
end if;
|
end if;
|
|
|
if reset_in = '0' then
|
if reset_in = '0' then
|
opcode_out <= opcode_reg;
|
opcode_out <= opcode_reg;
|
else
|
else
|
opcode_out <= ZERO;
|
opcode_out <= ZERO;
|
end if;
|
end if;
|
data_read <= datab;
|
data_read <= datab;
|
pause_out <= mem_pause or pause;
|
pause_out <= mem_pause or pause;
|
mem_byte_sel <= byte_sel_next;
|
mem_byte_sel <= byte_sel_next;
|
mem_address <= address_next;
|
mem_address <= address_next;
|
if write_next = '1' and setup_state /= STATE_FETCH then
|
if write_next = '1' and setup_state /= STATE_FETCH then
|
mem_write <= '1';
|
mem_write <= '1';
|
mem_data_w <= mem_data_w_v;
|
mem_data_w <= mem_data_w_v;
|
else
|
else
|
mem_write <= '0';
|
mem_write <= '0';
|
mem_data_w <= HIGH_Z; --ZERO;
|
mem_data_w <= HIGH_Z; --ZERO;
|
end if;
|
end if;
|
|
|
end process; --data_proc
|
end process; --data_proc
|
|
|
end; --architecture logic
|
end; --architecture logic
|
|
|
|
|