---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Plasma Misc. Package
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-- TITLE: Plasma Misc. Package
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/15/01
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-- DATE CREATED: 2/15/01
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-- FILENAME: mlite_pack.vhd
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-- FILENAME: mlite_pack.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Data types, constants, and add functions needed for the Plasma CPU.
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-- Data types, constants, and add functions needed for the Plasma CPU.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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package mlite_pack is
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package mlite_pack is
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constant ZERO : std_logic_vector(31 downto 0) :=
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constant ZERO : std_logic_vector(31 downto 0) :=
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"00000000000000000000000000000000";
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"00000000000000000000000000000000";
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constant ONES : std_logic_vector(31 downto 0) :=
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constant ONES : std_logic_vector(31 downto 0) :=
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"11111111111111111111111111111111";
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"11111111111111111111111111111111";
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--make HIGH_Z equal to ZERO if compiler complains
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--make HIGH_Z equal to ZERO if compiler complains
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constant HIGH_Z : std_logic_vector(31 downto 0) :=
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constant HIGH_Z : std_logic_vector(31 downto 0) :=
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"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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subtype alu_function_type is std_logic_vector(3 downto 0);
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subtype alu_function_type is std_logic_vector(3 downto 0);
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constant ALU_NOTHING : alu_function_type := "0000";
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constant ALU_NOTHING : alu_function_type := "0000";
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constant ALU_ADD : alu_function_type := "0001";
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constant ALU_ADD : alu_function_type := "0001";
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constant ALU_SUBTRACT : alu_function_type := "0010";
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constant ALU_SUBTRACT : alu_function_type := "0010";
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constant ALU_LESS_THAN : alu_function_type := "0011";
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constant ALU_LESS_THAN : alu_function_type := "0011";
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constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
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constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
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constant ALU_OR : alu_function_type := "0101";
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constant ALU_OR : alu_function_type := "0101";
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constant ALU_AND : alu_function_type := "0110";
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constant ALU_AND : alu_function_type := "0110";
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constant ALU_XOR : alu_function_type := "0111";
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constant ALU_XOR : alu_function_type := "0111";
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constant ALU_NOR : alu_function_type := "1000";
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constant ALU_NOR : alu_function_type := "1000";
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|
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subtype shift_function_type is std_logic_vector(1 downto 0);
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subtype shift_function_type is std_logic_vector(1 downto 0);
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constant SHIFT_NOTHING : shift_function_type := "00";
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constant SHIFT_NOTHING : shift_function_type := "00";
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constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
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constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
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constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
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constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
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constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
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constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
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subtype mult_function_type is std_logic_vector(3 downto 0);
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subtype mult_function_type is std_logic_vector(3 downto 0);
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constant MULT_NOTHING : mult_function_type := "0000";
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constant MULT_NOTHING : mult_function_type := "0000";
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constant MULT_READ_LO : mult_function_type := "0001";
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constant MULT_READ_LO : mult_function_type := "0001";
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constant MULT_READ_HI : mult_function_type := "0010";
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constant MULT_READ_HI : mult_function_type := "0010";
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constant MULT_WRITE_LO : mult_function_type := "0011";
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constant MULT_WRITE_LO : mult_function_type := "0011";
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constant MULT_WRITE_HI : mult_function_type := "0100";
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constant MULT_WRITE_HI : mult_function_type := "0100";
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constant MULT_MULT : mult_function_type := "0101";
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constant MULT_MULT : mult_function_type := "0101";
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constant MULT_SIGNED_MULT : mult_function_type := "0110";
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constant MULT_SIGNED_MULT : mult_function_type := "0110";
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constant MULT_DIVIDE : mult_function_type := "0111";
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constant MULT_DIVIDE : mult_function_type := "0111";
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constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
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constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
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subtype a_source_type is std_logic_vector(1 downto 0);
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subtype a_source_type is std_logic_vector(1 downto 0);
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constant A_FROM_REG_SOURCE : a_source_type := "00";
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constant A_FROM_REG_SOURCE : a_source_type := "00";
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constant A_FROM_IMM10_6 : a_source_type := "01";
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constant A_FROM_IMM10_6 : a_source_type := "01";
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constant A_FROM_PC : a_source_type := "10";
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constant A_FROM_PC : a_source_type := "10";
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subtype b_source_type is std_logic_vector(1 downto 0);
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subtype b_source_type is std_logic_vector(1 downto 0);
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constant B_FROM_REG_TARGET : b_source_type := "00";
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constant B_FROM_REG_TARGET : b_source_type := "00";
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constant B_FROM_IMM : b_source_type := "01";
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constant B_FROM_IMM : b_source_type := "01";
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constant B_FROM_SIGNED_IMM : b_source_type := "10";
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constant B_FROM_SIGNED_IMM : b_source_type := "10";
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constant B_FROM_IMMX4 : b_source_type := "11";
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constant B_FROM_IMMX4 : b_source_type := "11";
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subtype c_source_type is std_logic_vector(2 downto 0);
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subtype c_source_type is std_logic_vector(2 downto 0);
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constant C_FROM_NULL : c_source_type := "000";
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constant C_FROM_NULL : c_source_type := "000";
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constant C_FROM_ALU : c_source_type := "001";
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constant C_FROM_ALU : c_source_type := "001";
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constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
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constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
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constant C_FROM_MULT : c_source_type := "001"; --same as alu
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constant C_FROM_MULT : c_source_type := "001"; --same as alu
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constant C_FROM_MEMORY : c_source_type := "010";
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constant C_FROM_MEMORY : c_source_type := "010";
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constant C_FROM_PC : c_source_type := "011";
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constant C_FROM_PC : c_source_type := "011";
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constant C_FROM_PC_PLUS4 : c_source_type := "100";
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constant C_FROM_PC_PLUS4 : c_source_type := "100";
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constant C_FROM_IMM_SHIFT16: c_source_type := "101";
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constant C_FROM_IMM_SHIFT16: c_source_type := "101";
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constant C_FROM_REG_SOURCEN: c_source_type := "110";
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constant C_FROM_REG_SOURCEN: c_source_type := "110";
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subtype pc_source_type is std_logic_vector(1 downto 0);
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subtype pc_source_type is std_logic_vector(1 downto 0);
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constant FROM_INC4 : pc_source_type := "00";
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constant FROM_INC4 : pc_source_type := "00";
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constant FROM_OPCODE25_0 : pc_source_type := "01";
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constant FROM_OPCODE25_0 : pc_source_type := "01";
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constant FROM_BRANCH : pc_source_type := "10";
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constant FROM_BRANCH : pc_source_type := "10";
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constant FROM_LBRANCH : pc_source_type := "11";
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constant FROM_LBRANCH : pc_source_type := "11";
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subtype branch_function_type is std_logic_vector(2 downto 0);
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subtype branch_function_type is std_logic_vector(2 downto 0);
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constant BRANCH_LTZ : branch_function_type := "000";
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constant BRANCH_LTZ : branch_function_type := "000";
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constant BRANCH_LEZ : branch_function_type := "001";
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constant BRANCH_LEZ : branch_function_type := "001";
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constant BRANCH_EQ : branch_function_type := "010";
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constant BRANCH_EQ : branch_function_type := "010";
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constant BRANCH_NE : branch_function_type := "011";
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constant BRANCH_NE : branch_function_type := "011";
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constant BRANCH_GEZ : branch_function_type := "100";
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constant BRANCH_GEZ : branch_function_type := "100";
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constant BRANCH_GTZ : branch_function_type := "101";
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constant BRANCH_GTZ : branch_function_type := "101";
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constant BRANCH_YES : branch_function_type := "110";
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constant BRANCH_YES : branch_function_type := "110";
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constant BRANCH_NO : branch_function_type := "111";
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constant BRANCH_NO : branch_function_type := "111";
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-- mode(32=1,16=2,8=3), signed, write
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-- mode(32=1,16=2,8=3), signed, write
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subtype mem_source_type is std_logic_vector(3 downto 0);
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subtype mem_source_type is std_logic_vector(3 downto 0);
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constant MEM_FETCH : mem_source_type := "0000";
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constant MEM_FETCH : mem_source_type := "0000";
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constant MEM_READ32 : mem_source_type := "0100";
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constant MEM_READ32 : mem_source_type := "0100";
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constant MEM_WRITE32 : mem_source_type := "0101";
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constant MEM_WRITE32 : mem_source_type := "0101";
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constant MEM_READ16 : mem_source_type := "1000";
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constant MEM_READ16 : mem_source_type := "1000";
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constant MEM_READ16S : mem_source_type := "1010";
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constant MEM_READ16S : mem_source_type := "1010";
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constant MEM_WRITE16 : mem_source_type := "1001";
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constant MEM_WRITE16 : mem_source_type := "1001";
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constant MEM_READ8 : mem_source_type := "1100";
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constant MEM_READ8 : mem_source_type := "1100";
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constant MEM_READ8S : mem_source_type := "1110";
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constant MEM_READ8S : mem_source_type := "1110";
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constant MEM_WRITE8 : mem_source_type := "1101";
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constant MEM_WRITE8 : mem_source_type := "1101";
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|
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function bv_adder(a : in std_logic_vector;
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function bv_adder(a : in std_logic_vector;
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b : in std_logic_vector;
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b : in std_logic_vector;
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do_add: in std_logic) return std_logic_vector;
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do_add: in std_logic) return std_logic_vector;
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function bv_negate(a : in std_logic_vector) return std_logic_vector;
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function bv_negate(a : in std_logic_vector) return std_logic_vector;
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function bv_increment(a : in std_logic_vector(31 downto 2)
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function bv_increment(a : in std_logic_vector(31 downto 2)
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) return std_logic_vector;
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) return std_logic_vector;
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function bv_inc(a : in std_logic_vector
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function bv_inc(a : in std_logic_vector
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) return std_logic_vector;
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) return std_logic_vector;
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-- For Altera
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-- For Altera
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COMPONENT lpm_add_sub
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COMPONENT lpm_add_sub
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GENERIC (
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GENERIC (
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lpm_width : NATURAL;
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lpm_width : NATURAL;
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lpm_direction : STRING := "UNUSED";
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lpm_direction : STRING := "UNUSED";
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lpm_type : STRING;
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lpm_type : STRING;
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lpm_hint : STRING);
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lpm_hint : STRING);
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PORT (
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PORT (
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dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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add_sub : IN STD_LOGIC ;
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add_sub : IN STD_LOGIC ;
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datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
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result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
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END COMPONENT;
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END COMPONENT;
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-- For Altera
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-- For Altera
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COMPONENT lpm_ram_dp
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COMPONENT lpm_ram_dp
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GENERIC (
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GENERIC (
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lpm_width : NATURAL;
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lpm_width : NATURAL;
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lpm_widthad : NATURAL;
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lpm_widthad : NATURAL;
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rden_used : STRING;
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rden_used : STRING;
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intended_device_family : STRING;
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intended_device_family : STRING;
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lpm_indata : STRING;
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lpm_indata : STRING;
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lpm_wraddress_control : STRING;
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lpm_wraddress_control : STRING;
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lpm_rdaddress_control : STRING;
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lpm_rdaddress_control : STRING;
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lpm_outdata : STRING;
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lpm_outdata : STRING;
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use_eab : STRING;
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use_eab : STRING;
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lpm_type : STRING);
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lpm_type : STRING);
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PORT (
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PORT (
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wren : IN STD_LOGIC ;
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wren : IN STD_LOGIC ;
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wrclock : IN STD_LOGIC ;
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wrclock : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
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rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
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rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
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wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
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wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
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END COMPONENT;
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END COMPONENT;
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-- For Altera
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-- For Altera
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component LPM_RAM_DQ
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component LPM_RAM_DQ
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generic (
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generic (
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LPM_WIDTH : natural; -- MUST be greater than 0
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LPM_WIDTH : natural; -- MUST be greater than 0
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LPM_WIDTHAD : natural; -- MUST be greater than 0
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LPM_WIDTHAD : natural; -- MUST be greater than 0
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LPM_NUMWORDS : natural := 0;
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LPM_NUMWORDS : natural := 0;
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LPM_INDATA : string := "REGISTERED";
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LPM_INDATA : string := "REGISTERED";
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LPM_ADDRESS_CONTROL: string := "REGISTERED";
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LPM_ADDRESS_CONTROL: string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_FILE : string := "UNUSED";
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LPM_FILE : string := "UNUSED";
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LPM_TYPE : string := "LPM_RAM_DQ";
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LPM_TYPE : string := "LPM_RAM_DQ";
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USE_EAB : string := "OFF";
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USE_EAB : string := "OFF";
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INTENDED_DEVICE_FAMILY : string := "UNUSED";
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INTENDED_DEVICE_FAMILY : string := "UNUSED";
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LPM_HINT : string := "UNUSED");
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LPM_HINT : string := "UNUSED");
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port (
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port (
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DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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INCLOCK : in std_logic := '0';
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INCLOCK : in std_logic := '0';
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OUTCLOCK : in std_logic := '0';
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OUTCLOCK : in std_logic := '0';
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WE : in std_logic;
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WE : in std_logic;
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
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end component;
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end component;
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|
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-- For Xilinx
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-- For Xilinx
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component ramb4_s16_s16
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component ramb4_s16_s16
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port (
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port (
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clka : in std_logic;
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clka : in std_logic;
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rsta : in std_logic;
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rsta : in std_logic;
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addra : in std_logic_vector;
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addra : in std_logic_vector;
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dia : in std_logic_vector;
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dia : in std_logic_vector;
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ena : in std_logic;
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ena : in std_logic;
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wea : in std_logic;
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wea : in std_logic;
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doa : out std_logic_vector;
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doa : out std_logic_vector;
|
|
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clkb : in std_logic;
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clkb : in std_logic;
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rstb : in std_logic;
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rstb : in std_logic;
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addrb : in std_logic_vector;
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addrb : in std_logic_vector;
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dib : in std_logic_vector;
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dib : in std_logic_vector;
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enb : in std_logic;
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enb : in std_logic;
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web : in std_logic);
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web : in std_logic);
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end component;
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end component;
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|
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-- For Xilinx
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-- For Xilinx
|
component reg_file_dp_ram
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component reg_file_dp_ram
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port (
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port (
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addra : IN std_logic_VECTOR(4 downto 0);
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addra : IN std_logic_VECTOR(4 downto 0);
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addrb : IN std_logic_VECTOR(4 downto 0);
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addrb : IN std_logic_VECTOR(4 downto 0);
|
clka : IN std_logic;
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clka : IN std_logic;
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clkb : IN std_logic;
|
clkb : IN std_logic;
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dinb : IN std_logic_VECTOR(31 downto 0);
|
dinb : IN std_logic_VECTOR(31 downto 0);
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douta : OUT std_logic_VECTOR(31 downto 0);
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douta : OUT std_logic_VECTOR(31 downto 0);
|
web : IN std_logic);
|
web : IN std_logic);
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end component;
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end component;
|
|
|
-- For Xilinx
|
-- For Xilinx
|
component reg_file_dp_ram_xc4000xla
|
component reg_file_dp_ram_xc4000xla
|
port (
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port (
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A : IN std_logic_vector(4 DOWNTO 0);
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A : IN std_logic_vector(4 DOWNTO 0);
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DI : IN std_logic_vector(31 DOWNTO 0);
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DI : IN std_logic_vector(31 DOWNTO 0);
|
WR_EN : IN std_logic;
|
WR_EN : IN std_logic;
|
WR_CLK : IN std_logic;
|
WR_CLK : IN std_logic;
|
DPRA : IN std_logic_vector(4 DOWNTO 0);
|
DPRA : IN std_logic_vector(4 DOWNTO 0);
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SPO : OUT std_logic_vector(31 DOWNTO 0);
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SPO : OUT std_logic_vector(31 DOWNTO 0);
|
DPO : OUT std_logic_vector(31 DOWNTO 0));
|
DPO : OUT std_logic_vector(31 DOWNTO 0));
|
end component;
|
end component;
|
|
|
component pc_next
|
component pc_next
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pc_new : in std_logic_vector(31 downto 2);
|
pc_new : in std_logic_vector(31 downto 2);
|
take_branch : in std_logic;
|
take_branch : in std_logic;
|
pause_in : in std_logic;
|
pause_in : in std_logic;
|
opcode25_0 : in std_logic_vector(25 downto 0);
|
opcode25_0 : in std_logic_vector(25 downto 0);
|
pc_source : in pc_source_type;
|
pc_source : in pc_source_type;
|
pc_future : out std_logic_vector(31 downto 2);
|
pc_future : out std_logic_vector(31 downto 2);
|
pc_current : out std_logic_vector(31 downto 2);
|
pc_current : out std_logic_vector(31 downto 2);
|
pc_plus4 : out std_logic_vector(31 downto 2));
|
pc_plus4 : out std_logic_vector(31 downto 2));
|
end component;
|
end component;
|
|
|
component mem_ctrl
|
component mem_ctrl
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pause_in : in std_logic;
|
pause_in : in std_logic;
|
nullify_op : in std_logic;
|
nullify_op : in std_logic;
|
address_pc : in std_logic_vector(31 downto 2);
|
address_pc : in std_logic_vector(31 downto 2);
|
opcode_out : out std_logic_vector(31 downto 0);
|
opcode_out : out std_logic_vector(31 downto 0);
|
|
|
address_in : in std_logic_vector(31 downto 0);
|
address_in : in std_logic_vector(31 downto 0);
|
mem_source : in mem_source_type;
|
mem_source : in mem_source_type;
|
data_write : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic;
|
pause_out : out std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 2);
|
mem_address : out std_logic_vector(31 downto 2);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_byte_we : out std_logic_vector(3 downto 0));
|
mem_byte_we : out std_logic_vector(3 downto 0));
|
end component;
|
end component;
|
|
|
component control
|
component control
|
port(opcode : in std_logic_vector(31 downto 0);
|
port(opcode : in std_logic_vector(31 downto 0);
|
intr_signal : in std_logic;
|
intr_signal : in std_logic;
|
rs_index : out std_logic_vector(5 downto 0);
|
rs_index : out std_logic_vector(5 downto 0);
|
rt_index : out std_logic_vector(5 downto 0);
|
rt_index : out std_logic_vector(5 downto 0);
|
rd_index : out std_logic_vector(5 downto 0);
|
rd_index : out std_logic_vector(5 downto 0);
|
imm_out : out std_logic_vector(15 downto 0);
|
imm_out : out std_logic_vector(15 downto 0);
|
alu_func : out alu_function_type;
|
alu_func : out alu_function_type;
|
shift_func : out shift_function_type;
|
shift_func : out shift_function_type;
|
mult_func : out mult_function_type;
|
mult_func : out mult_function_type;
|
branch_func : out branch_function_type;
|
branch_func : out branch_function_type;
|
a_source_out : out a_source_type;
|
a_source_out : out a_source_type;
|
b_source_out : out b_source_type;
|
b_source_out : out b_source_type;
|
c_source_out : out c_source_type;
|
c_source_out : out c_source_type;
|
pc_source_out: out pc_source_type;
|
pc_source_out: out pc_source_type;
|
mem_source_out:out mem_source_type);
|
mem_source_out:out mem_source_type;
|
|
exception_out: out std_logic);
|
end component;
|
end component;
|
|
|
component reg_bank
|
component reg_bank
|
generic(memory_type : string := "XILINX_16X");
|
generic(memory_type : string := "XILINX_16X");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
pause : in std_logic;
|
pause : in std_logic;
|
rs_index : in std_logic_vector(5 downto 0);
|
rs_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
rd_index : in std_logic_vector(5 downto 0);
|
rd_index : in std_logic_vector(5 downto 0);
|
reg_source_out : out std_logic_vector(31 downto 0);
|
reg_source_out : out std_logic_vector(31 downto 0);
|
reg_target_out : out std_logic_vector(31 downto 0);
|
reg_target_out : out std_logic_vector(31 downto 0);
|
reg_dest_new : in std_logic_vector(31 downto 0);
|
reg_dest_new : in std_logic_vector(31 downto 0);
|
intr_enable : out std_logic);
|
intr_enable : out std_logic);
|
end component;
|
end component;
|
|
|
component bus_mux
|
component bus_mux
|
port(imm_in : in std_logic_vector(15 downto 0);
|
port(imm_in : in std_logic_vector(15 downto 0);
|
reg_source : in std_logic_vector(31 downto 0);
|
reg_source : in std_logic_vector(31 downto 0);
|
a_mux : in a_source_type;
|
a_mux : in a_source_type;
|
a_out : out std_logic_vector(31 downto 0);
|
a_out : out std_logic_vector(31 downto 0);
|
|
|
reg_target : in std_logic_vector(31 downto 0);
|
reg_target : in std_logic_vector(31 downto 0);
|
b_mux : in b_source_type;
|
b_mux : in b_source_type;
|
b_out : out std_logic_vector(31 downto 0);
|
b_out : out std_logic_vector(31 downto 0);
|
|
|
c_bus : in std_logic_vector(31 downto 0);
|
c_bus : in std_logic_vector(31 downto 0);
|
c_memory : in std_logic_vector(31 downto 0);
|
c_memory : in std_logic_vector(31 downto 0);
|
c_pc : in std_logic_vector(31 downto 2);
|
c_pc : in std_logic_vector(31 downto 2);
|
c_pc_plus4 : in std_logic_vector(31 downto 2);
|
c_pc_plus4 : in std_logic_vector(31 downto 2);
|
c_mux : in c_source_type;
|
c_mux : in c_source_type;
|
reg_dest_out : out std_logic_vector(31 downto 0);
|
reg_dest_out : out std_logic_vector(31 downto 0);
|
|
|
branch_func : in branch_function_type;
|
branch_func : in branch_function_type;
|
take_branch : out std_logic);
|
take_branch : out std_logic);
|
end component;
|
end component;
|
|
|
component alu
|
component alu
|
generic(alu_type : string := "DEFAULT");
|
generic(alu_type : string := "DEFAULT");
|
port(a_in : in std_logic_vector(31 downto 0);
|
port(a_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
alu_function : in alu_function_type;
|
alu_function : in alu_function_type;
|
c_alu : out std_logic_vector(31 downto 0));
|
c_alu : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component shifter
|
component shifter
|
generic(shifter_type : string := "DEFAULT" );
|
generic(shifter_type : string := "DEFAULT" );
|
port(value : in std_logic_vector(31 downto 0);
|
port(value : in std_logic_vector(31 downto 0);
|
shift_amount : in std_logic_vector(4 downto 0);
|
shift_amount : in std_logic_vector(4 downto 0);
|
shift_func : in shift_function_type;
|
shift_func : in shift_function_type;
|
c_shift : out std_logic_vector(31 downto 0));
|
c_shift : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component mult
|
component mult
|
generic(mult_type : string := "DEFAULT");
|
generic(mult_type : string := "DEFAULT");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
a, b : in std_logic_vector(31 downto 0);
|
a, b : in std_logic_vector(31 downto 0);
|
mult_func : in mult_function_type;
|
mult_func : in mult_function_type;
|
c_mult : out std_logic_vector(31 downto 0);
|
c_mult : out std_logic_vector(31 downto 0);
|
pause_out : out std_logic);
|
pause_out : out std_logic);
|
end component;
|
end component;
|
|
|
component pipeline
|
component pipeline
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
a_bus : in std_logic_vector(31 downto 0);
|
a_bus : in std_logic_vector(31 downto 0);
|
a_busD : out std_logic_vector(31 downto 0);
|
a_busD : out std_logic_vector(31 downto 0);
|
b_bus : in std_logic_vector(31 downto 0);
|
b_bus : in std_logic_vector(31 downto 0);
|
b_busD : out std_logic_vector(31 downto 0);
|
b_busD : out std_logic_vector(31 downto 0);
|
alu_func : in alu_function_type;
|
alu_func : in alu_function_type;
|
alu_funcD : out alu_function_type;
|
alu_funcD : out alu_function_type;
|
shift_func : in shift_function_type;
|
shift_func : in shift_function_type;
|
shift_funcD : out shift_function_type;
|
shift_funcD : out shift_function_type;
|
mult_func : in mult_function_type;
|
mult_func : in mult_function_type;
|
mult_funcD : out mult_function_type;
|
mult_funcD : out mult_function_type;
|
reg_dest : in std_logic_vector(31 downto 0);
|
reg_dest : in std_logic_vector(31 downto 0);
|
reg_destD : out std_logic_vector(31 downto 0);
|
reg_destD : out std_logic_vector(31 downto 0);
|
rd_index : in std_logic_vector(5 downto 0);
|
rd_index : in std_logic_vector(5 downto 0);
|
rd_indexD : out std_logic_vector(5 downto 0);
|
rd_indexD : out std_logic_vector(5 downto 0);
|
|
|
rs_index : in std_logic_vector(5 downto 0);
|
rs_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
rt_index : in std_logic_vector(5 downto 0);
|
pc_source : in pc_source_type;
|
pc_source : in pc_source_type;
|
mem_source : in mem_source_type;
|
mem_source : in mem_source_type;
|
a_source : in a_source_type;
|
a_source : in a_source_type;
|
b_source : in b_source_type;
|
b_source : in b_source_type;
|
c_source : in c_source_type;
|
c_source : in c_source_type;
|
c_bus : in std_logic_vector(31 downto 0);
|
c_bus : in std_logic_vector(31 downto 0);
|
pause_any : in std_logic;
|
pause_any : in std_logic;
|
pause_pipeline : out std_logic);
|
pause_pipeline : out std_logic);
|
end component;
|
end component;
|
|
|
component mlite_cpu
|
component mlite_cpu
|
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
|
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
|
mult_type : string := "DEFAULT";
|
mult_type : string := "DEFAULT";
|
shifter_type : string := "DEFAULT";
|
shifter_type : string := "DEFAULT";
|
alu_type : string := "DEFAULT";
|
alu_type : string := "DEFAULT";
|
pipeline_stages : natural := 3); --3 or 4
|
pipeline_stages : natural := 3); --3 or 4
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_address : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_w : out std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
mem_byte_we : out std_logic_vector(3 downto 0);
|
mem_byte_we : out std_logic_vector(3 downto 0);
|
mem_pause : in std_logic);
|
mem_pause : in std_logic);
|
end component;
|
end component;
|
|
|
component ram
|
component ram
|
generic(memory_type : string := "DEFAULT");
|
generic(memory_type : string := "DEFAULT");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
write_byte_enable : in std_logic_vector(3 downto 0);
|
write_byte_enable : in std_logic_vector(3 downto 0);
|
address : in std_logic_vector(31 downto 2);
|
address : in std_logic_vector(31 downto 2);
|
data_write : in std_logic_vector(31 downto 0);
|
data_write : in std_logic_vector(31 downto 0);
|
data_read : out std_logic_vector(31 downto 0));
|
data_read : out std_logic_vector(31 downto 0));
|
end component; --ram
|
end component; --ram
|
|
|
component uart
|
component uart
|
generic(log_file : string := "UNUSED");
|
generic(log_file : string := "UNUSED");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
enable_read : in std_logic;
|
enable_read : in std_logic;
|
enable_write : in std_logic;
|
enable_write : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
busy_write : out std_logic;
|
busy_write : out std_logic;
|
data_avail : out std_logic);
|
data_avail : out std_logic);
|
end component; --uart
|
end component; --uart
|
|
|
component plasma
|
component plasma
|
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
|
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
|
log_file : string := "UNUSED");
|
log_file : string := "UNUSED");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
|
|
address : out std_logic_vector(31 downto 2);
|
address : out std_logic_vector(31 downto 2);
|
data_write : out std_logic_vector(31 downto 0);
|
data_write : out std_logic_vector(31 downto 0);
|
data_read : in std_logic_vector(31 downto 0);
|
data_read : in std_logic_vector(31 downto 0);
|
write_byte_enable : out std_logic_vector(3 downto 0);
|
write_byte_enable : out std_logic_vector(3 downto 0);
|
mem_pause_in : in std_logic;
|
mem_pause_in : in std_logic;
|
|
|
gpio0_out : out std_logic_vector(31 downto 0);
|
gpio0_out : out std_logic_vector(31 downto 0);
|
gpioA_in : in std_logic_vector(31 downto 0));
|
gpioA_in : in std_logic_vector(31 downto 0));
|
end component; --plasma
|
end component; --plasma
|
|
|
end; --package mlite_pack
|
end; --package mlite_pack
|
|
|
|
|
package body mlite_pack is
|
package body mlite_pack is
|
|
|
function bv_adder(a : in std_logic_vector;
|
function bv_adder(a : in std_logic_vector;
|
b : in std_logic_vector;
|
b : in std_logic_vector;
|
do_add: in std_logic) return std_logic_vector is
|
do_add: in std_logic) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable bb : std_logic_vector(a'length-1 downto 0);
|
variable bb : std_logic_vector(a'length-1 downto 0);
|
variable result : std_logic_vector(a'length downto 0);
|
variable result : std_logic_vector(a'length downto 0);
|
begin
|
begin
|
if do_add = '1' then
|
if do_add = '1' then
|
bb := b;
|
bb := b;
|
carry_in := '0';
|
carry_in := '0';
|
else
|
else
|
bb := not b;
|
bb := not b;
|
carry_in := '1';
|
carry_in := '1';
|
end if;
|
end if;
|
for index in 0 to a'length-1 loop
|
for index in 0 to a'length-1 loop
|
result(index) := a(index) xor bb(index) xor carry_in;
|
result(index) := a(index) xor bb(index) xor carry_in;
|
carry_in := (carry_in and (a(index) or bb(index))) or
|
carry_in := (carry_in and (a(index) or bb(index))) or
|
(a(index) and bb(index));
|
(a(index) and bb(index));
|
end loop;
|
end loop;
|
result(a'length) := carry_in xnor do_add;
|
result(a'length) := carry_in xnor do_add;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable not_a : std_logic_vector(a'length-1 downto 0);
|
variable not_a : std_logic_vector(a'length-1 downto 0);
|
variable result : std_logic_vector(a'length-1 downto 0);
|
variable result : std_logic_vector(a'length-1 downto 0);
|
begin
|
begin
|
not_a := not a;
|
not_a := not a;
|
carry_in := '1';
|
carry_in := '1';
|
for index in a'reverse_range loop
|
for index in a'reverse_range loop
|
result(index) := not_a(index) xor carry_in;
|
result(index) := not_a(index) xor carry_in;
|
carry_in := carry_in and not_a(index);
|
carry_in := carry_in and not_a(index);
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(31 downto 2);
|
variable result : std_logic_vector(31 downto 2);
|
begin
|
begin
|
carry_in := '1';
|
carry_in := '1';
|
for index in 2 to 31 loop
|
for index in 2 to 31 loop
|
result(index) := a(index) xor carry_in;
|
result(index) := a(index) xor carry_in;
|
carry_in := a(index) and carry_in;
|
carry_in := a(index) and carry_in;
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_inc(a : in std_logic_vector
|
function bv_inc(a : in std_logic_vector
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(a'length-1 downto 0);
|
variable result : std_logic_vector(a'length-1 downto 0);
|
begin
|
begin
|
carry_in := '1';
|
carry_in := '1';
|
for index in 0 to a'length-1 loop
|
for index in 0 to a'length-1 loop
|
result(index) := a(index) xor carry_in;
|
result(index) := a(index) xor carry_in;
|
carry_in := a(index) and carry_in;
|
carry_in := a(index) and carry_in;
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
end; --package body
|
end; --package body
|
|
|
|
|
|
|