---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Multiplication and Division Unit
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-- TITLE: Multiplication and Division Unit
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mult.vhd
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-- FILENAME: mult.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: MIPS CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the multiplication and division unit.
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-- Implements the multiplication and division unit.
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-- Normally takes 32 clock cycles.
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-- Normally takes 32 clock cycles.
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-- if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles.
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-- if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles.
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-- if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles.
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-- if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mips_pack.all;
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entity mult is
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entity mult is
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port(clk : in std_logic;
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port(clk : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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pause_out : out std_logic);
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end; --entity mult
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end; --entity mult
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architecture logic of mult is
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architecture logic of mult is
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-- type mult_function_type is (
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-- type mult_function_type is (
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-- mult_nothing, mult_read_lo, mult_read_hi, mult_write_lo,
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-- mult_nothing, mult_read_lo, mult_read_hi, mult_write_lo,
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-- mult_write_hi, mult_mult, mult_divide, mult_signed_divide);
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-- mult_write_hi, mult_mult, mult_divide, mult_signed_divide);
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signal do_div_reg : std_logic;
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signal do_div_reg : std_logic;
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signal do_signed_reg : std_logic;
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signal do_signed_reg : std_logic;
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signal count_reg : std_logic_vector(5 downto 0);
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signal count_reg : std_logic_vector(5 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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-- signal sum_out : std_logic_vector(32 downto 0);
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begin
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begin
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, a, b, mult_func,
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mult_proc: process(clk, a, b, mult_func,
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do_div_reg, do_signed_reg, count_reg,
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do_div_reg, do_signed_reg, count_reg,
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reg_a, reg_b, answer_reg)
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reg_a, reg_b, answer_reg)
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variable do_div_temp : std_logic;
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variable do_div_temp : std_logic;
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variable do_signed_temp : std_logic;
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variable do_signed_temp : std_logic;
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variable count_temp : std_logic_vector(5 downto 0);
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variable count_temp : std_logic_vector(5 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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variable answer_temp : std_logic_vector(31 downto 0);
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variable answer_temp : std_logic_vector(31 downto 0);
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variable aa, bb : std_logic_vector(32 downto 0);
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variable aa, bb : std_logic_vector(32 downto 0);
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variable sum : std_logic_vector(32 downto 0);
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variable sum : std_logic_vector(32 downto 0);
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variable start : std_logic;
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable do_hi : std_logic;
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begin
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begin
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do_div_temp := do_div_reg;
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do_div_temp := do_div_reg;
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do_signed_temp := do_signed_reg;
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do_signed_temp := do_signed_reg;
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count_temp := count_reg;
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count_temp := count_reg;
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a_temp := reg_a;
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a_temp := reg_a;
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b_temp := reg_b;
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b_temp := reg_b;
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answer_temp := answer_reg;
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answer_temp := answer_reg;
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aa := '0' & ZERO;
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aa := '0' & ZERO;
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bb := '0' & ZERO;
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bb := '0' & ZERO;
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sum := '0' & ZERO;
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sum := '0' & ZERO;
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start := '0';
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start := '0';
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do_write := '0';
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do_write := '0';
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do_hi := '0';
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do_hi := '0';
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case mult_func is
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case mult_func is
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when mult_read_lo =>
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when mult_read_lo =>
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when mult_read_hi =>
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when mult_read_hi =>
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do_hi := '1';
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do_hi := '1';
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when mult_write_lo =>
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when mult_write_lo =>
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do_write := '1';
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do_write := '1';
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when mult_write_hi =>
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when mult_write_hi =>
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do_write := '1';
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do_write := '1';
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do_hi := '1';
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do_hi := '1';
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when mult_mult =>
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when mult_mult =>
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start := '1';
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start := '1';
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do_div_temp := '0';
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do_div_temp := '0';
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when mult_divide =>
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when mult_divide =>
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start := '1';
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start := '1';
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do_div_temp := '1';
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do_div_temp := '1';
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do_signed_temp := '0';
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do_signed_temp := '0';
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when mult_signed_divide =>
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when mult_signed_divide =>
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start := '1';
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start := '1';
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do_div_temp := '1';
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do_div_temp := '1';
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do_signed_temp := '1';
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do_signed_temp := a(31) xor b(31);
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when others =>
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when others =>
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end case;
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end case;
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if start = '1' then
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if start = '1' then
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count_temp := "000000";
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count_temp := "000000";
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a_temp := a;
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answer_temp := ZERO;
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answer_temp := ZERO;
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if do_div_temp = '1' then
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if do_div_temp = '1' then
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b_temp(63) := '0';
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b_temp(63) := '0';
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if do_signed_temp = '0' or b(31) = '0' then
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if mult_func /= mult_signed_divide or b(31) = '0' then
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b_temp(62 downto 31) := b;
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b_temp(62 downto 31) := b;
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else
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else
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b_temp(62 downto 31) := bv_negate(b);
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b_temp(62 downto 31) := bv_negate(b);
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end if;
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if mult_func /= mult_signed_divide or a(31) = '0' then
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a_temp := a;
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else
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a_temp := bv_negate(a);
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a_temp := bv_negate(a);
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end if;
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end if;
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b_temp(30 downto 0) := ZERO(30 downto 0);
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b_temp(30 downto 0) := ZERO(30 downto 0);
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if do_signed_temp = '1' and a(31) = b(31) then
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do_signed_temp := '0';
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end if;
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else --multiply
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else --multiply
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a_temp := a;
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b_temp := ZERO & b;
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b_temp := ZERO & b;
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end if;
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end if;
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elsif do_write = '1' then
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elsif do_write = '1' then
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if do_hi = '0' then
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if do_hi = '0' then
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b_temp(31 downto 0) := a;
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b_temp(31 downto 0) := a;
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else
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else
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b_temp(63 downto 32) := a;
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b_temp(63 downto 32) := a;
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end if;
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end if;
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end if;
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end if;
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if do_div_reg = '1' then
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if do_div_reg = '1' then
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bb := reg_b(32 downto 0);
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bb := reg_b(32 downto 0);
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else
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else
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bb := '0' & reg_b(63 downto 32);
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bb := '0' & reg_b(63 downto 32);
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end if;
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end if;
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aa := do_signed_reg & reg_a;
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aa := '0' & reg_a;
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sum := bv_adder(aa, bb, do_div_reg);
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sum := bv_adder(aa, bb, do_div_reg);
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-- sum := bv_adder_lookahead(aa, bb, do_div_reg);
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-- sum := bv_adder_lookahead(aa, bb, do_div_reg);
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if count_reg(5) = '0' and start = '0' then
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if count_reg(5) = '0' and start = '0' then
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count_temp := bv_inc6(count_reg);
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count_temp := bv_inc6(count_reg);
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if do_div_reg = '1' then
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if do_div_reg = '1' then
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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if reg_b(63 downto 32) = ZERO and sum(32) = do_signed_reg then
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if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
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a_temp := sum(31 downto 0); --aa=aa-bb;
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a_temp := sum(31 downto 0); --aa=aa-bb;
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answer_temp(0) := '1';
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answer_temp(0) := '1';
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else
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else
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answer_temp(0) := '0';
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answer_temp(0) := '0';
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end if;
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end if;
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if count_reg /= "011111" then
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if count_reg /= "011111" then
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b_temp(62 downto 0) := reg_b(63 downto 1);
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b_temp(62 downto 0) := reg_b(63 downto 1);
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else
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else
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b_temp(63 downto 32) := a_temp;
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b_temp(63 downto 32) := a_temp;
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if do_signed_reg = '0' then
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b_temp(31 downto 0) := answer_temp;
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b_temp(31 downto 0) := answer_temp;
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else
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b_temp(31 downto 0) := bv_negate(answer_temp);
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end if;
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end if;
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end if;
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else -- mult_mode
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else -- mult_mode
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if reg_b(0) = '1' then
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if reg_b(0) = '1' then
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b_temp(63 downto 31) := sum;
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b_temp(63 downto 31) := sum;
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else
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else
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b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
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b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
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end if;
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end if;
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b_temp(30 downto 0) := reg_b(31 downto 1);
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b_temp(30 downto 0) := reg_b(31 downto 1);
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if count_reg = "010000" and --early stop
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if count_reg = "010000" and --early stop
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(47 downto 16);
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b_temp(31 downto 0) := reg_b(47 downto 16);
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end if;
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end if;
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if count_reg = "001000" and --early stop
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if count_reg = "001000" and --early stop
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(55 downto 24);
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b_temp(31 downto 0) := reg_b(55 downto 24);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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do_div_reg <= do_div_temp;
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do_div_reg <= do_div_temp;
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do_signed_reg <= do_signed_temp;
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do_signed_reg <= do_signed_temp;
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count_reg <= count_temp;
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count_reg <= count_temp;
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reg_a <= a_temp;
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reg_a <= a_temp;
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reg_b <= b_temp;
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reg_b <= b_temp;
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answer_reg <= answer_temp;
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answer_reg <= answer_temp;
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end if;
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end if;
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if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
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if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
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pause_out <= '1';
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pause_out <= '1';
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else
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else
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pause_out <= '0';
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pause_out <= '0';
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end if;
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end if;
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if mult_func = mult_read_lo then
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if mult_func = mult_read_lo then
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c_mult <= reg_b(31 downto 0);
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c_mult <= reg_b(31 downto 0);
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elsif mult_func = mult_read_hi then
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elsif mult_func = mult_read_hi then
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c_mult <= reg_b(63 downto 32);
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c_mult <= reg_b(63 downto 32);
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else
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else
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c_mult <= ZERO;
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c_mult <= ZERO;
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end if;
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end if;
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-- sum_out <= sum;
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end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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