---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Pipeline
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-- TITLE: Pipeline
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/24/02
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-- DATE CREATED: 6/24/02
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-- FILENAME: pipeline.vhd
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-- FILENAME: pipeline.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Controls the three stage pipeline by delaying the signals:
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-- Controls the three stage pipeline by delaying the signals:
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-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
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-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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--Note: sigD <= sig after rising_edge(clk)
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--Note: sigD <= sig after rising_edge(clk)
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entity pipeline is
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entity pipeline is
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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a_bus : in std_logic_vector(31 downto 0);
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a_bus : in std_logic_vector(31 downto 0);
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a_busD : out std_logic_vector(31 downto 0);
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a_busD : out std_logic_vector(31 downto 0);
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b_bus : in std_logic_vector(31 downto 0);
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b_bus : in std_logic_vector(31 downto 0);
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b_busD : out std_logic_vector(31 downto 0);
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b_busD : out std_logic_vector(31 downto 0);
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alu_func : in alu_function_type;
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alu_func : in alu_function_type;
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alu_funcD : out alu_function_type;
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alu_funcD : out alu_function_type;
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shift_func : in shift_function_type;
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shift_func : in shift_function_type;
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shift_funcD : out shift_function_type;
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shift_funcD : out shift_function_type;
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mult_func : in mult_function_type;
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mult_func : in mult_function_type;
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mult_funcD : out mult_function_type;
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mult_funcD : out mult_function_type;
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reg_dest : in std_logic_vector(31 downto 0);
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reg_dest : in std_logic_vector(31 downto 0);
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reg_destD : out std_logic_vector(31 downto 0);
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reg_destD : out std_logic_vector(31 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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rd_indexD : out std_logic_vector(5 downto 0);
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rd_indexD : out std_logic_vector(5 downto 0);
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rs_index : in std_logic_vector(5 downto 0);
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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pc_source : in pc_source_type;
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pc_source : in pc_source_type;
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mem_source : in mem_source_type;
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mem_source : in mem_source_type;
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a_source : in a_source_type;
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a_source : in a_source_type;
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b_source : in b_source_type;
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b_source : in b_source_type;
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c_source : in c_source_type;
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c_source : in c_source_type;
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c_bus : in std_logic_vector(31 downto 0);
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c_bus : in std_logic_vector(31 downto 0);
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take_branch : in std_logic;
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take_branch : in std_logic;
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take_branchD : out std_logic;
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take_branchD : out std_logic;
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pause_any : in std_logic;
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pause_any : in std_logic;
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pause_pipeline : out std_logic);
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pause_pipeline : out std_logic);
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end; --entity pipeline
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end; --entity pipeline
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architecture logic of pipeline is
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architecture logic of pipeline is
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signal rd_index_reg : std_logic_vector(5 downto 0);
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signal rd_index_reg : std_logic_vector(5 downto 0);
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signal reg_dest_reg : std_logic_vector(31 downto 0);
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signal reg_dest_reg : std_logic_vector(31 downto 0);
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signal c_source_reg : c_source_type;
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signal c_source_reg : c_source_type;
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signal pause_reg : std_logic;
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signal pause_reg : std_logic;
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begin
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begin
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--When operating in three stage pipeline mode, the following signals
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--When operating in three stage pipeline mode, the following signals
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--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
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--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
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--c_source, and rd_index.
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--c_source, and rd_index.
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pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
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pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
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rd_index, rd_index_reg, pause_any, pause_reg,
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rd_index, rd_index_reg, pause_any, pause_reg,
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take_branch, rs_index, rt_index,
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take_branch, rs_index, rt_index,
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pc_source, mem_source, c_source, c_source_reg,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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reg_dest, reg_dest_reg)
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reg_dest, reg_dest_reg, c_bus)
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variable pause_mult_clock : std_logic;
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variable pause_mult_clock : std_logic;
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begin
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begin
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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mem_source /= mem_fetch or
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mem_source /= mem_fetch or
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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pause_mult_clock := '1';
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pause_mult_clock := '1';
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else
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else
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pause_mult_clock := '0';
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pause_mult_clock := '0';
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end if;
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end if;
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pause_pipeline <= pause_mult_clock and pause_reg;
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pause_pipeline <= pause_mult_clock and pause_reg;
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take_branchD <= take_branch and not pause_any;
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take_branchD <= take_branch and not pause_any;
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rd_indexD <= rd_index_reg;
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rd_indexD <= rd_index_reg;
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if c_source_reg = c_from_alu then
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if c_source_reg = c_from_alu then
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reg_destD <= c_bus;
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reg_destD <= c_bus;
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else
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else
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reg_destD <= reg_dest_reg;
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reg_destD <= reg_dest_reg;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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(a_source /= a_from_reg_source or pause_reg = '0') then
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(a_source /= a_from_reg_source or pause_reg = '0') then
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a_busD <= a_bus;
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a_busD <= a_bus;
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elsif c_source_reg = c_from_alu then
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elsif c_source_reg = c_from_alu then
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a_busD <= c_bus; --rs from previous operation (bypass stage)
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a_busD <= c_bus; --rs from previous operation (bypass stage)
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else
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else
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a_busD <= reg_dest_reg;
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a_busD <= reg_dest_reg;
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end if;
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end if;
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if (rt_index = "000000" or rt_index /= rd_index_reg) or
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if (rt_index = "000000" or rt_index /= rd_index_reg) or
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(b_source /= b_from_reg_target or pause_reg = '0') then
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(b_source /= b_from_reg_target or pause_reg = '0') then
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b_busD <= b_bus;
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b_busD <= b_bus;
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elsif c_source_reg = c_from_alu then
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elsif c_source_reg = c_from_alu then
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b_busD <= c_bus; --rt from previous operation
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b_busD <= c_bus; --rt from previous operation
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else
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else
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b_busD <= reg_dest_reg;
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b_busD <= reg_dest_reg;
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end if;
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end if;
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alu_funcD <= alu_func;
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alu_funcD <= alu_func;
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shift_funcD <= shift_func;
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shift_funcD <= shift_func;
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mult_funcD <= mult_func;
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mult_funcD <= mult_func;
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reg_dest_reg <= reg_dest;
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reg_dest_reg <= reg_dest;
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c_source_reg <= c_source;
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c_source_reg <= c_source;
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end if;
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end if;
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if reset = '1' then
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if reset = '1' then
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pause_reg <= '1';
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pause_reg <= '1';
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rd_index_reg <= "000000";
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rd_index_reg <= "000000";
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if pause_reg = '0' and pause_any = '0' then
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if pause_reg = '0' and pause_any = '0' then
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pause_reg <= '1'; --enable pause_pipeline
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pause_reg <= '1'; --enable pause_pipeline
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elsif pause_mult_clock = '1' then
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elsif pause_mult_clock = '1' then
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pause_reg <= '0'; --disable pause_pipeline
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pause_reg <= '0'; --disable pause_pipeline
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end if;
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end if;
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rd_index_reg <= rd_index;
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rd_index_reg <= rd_index;
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end if;
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end if;
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end process; --pipeline3
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end process; --pipeline3
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end; --logic
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end; --logic
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