---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Plasma (CPU core with memory)
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-- TITLE: Plasma (CPU core with memory)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/4/02
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-- DATE CREATED: 6/4/02
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-- FILENAME: plasma.vhd
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-- FILENAME: plasma.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity combines the CPU core with memory and a UART.
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-- This entity combines the CPU core with memory and a UART.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity plasma is
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entity plasma is
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generic(memory_type : string := "ALTERA";
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generic(memory_type : string := "ALTERA";
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log_file : string := "UNUSED");
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log_file : string := "UNUSED");
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port(clk_in : in std_logic;
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port(clk_in : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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intr_in : in std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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mem_address_out : out std_logic_vector(31 downto 0);
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mem_address_out : out std_logic_vector(31 downto 0);
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mem_data : out std_logic_vector(31 downto 0);
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mem_data : out std_logic_vector(31 downto 0);
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mem_byte_sel_out : out std_logic_vector(3 downto 0);
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mem_byte_sel_out : out std_logic_vector(3 downto 0);
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mem_write_out : out std_logic;
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mem_write_out : out std_logic;
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mem_pause_in : in std_logic);
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mem_pause_in : in std_logic);
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end; --entity plasma
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end; --entity plasma
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architecture logic of plasma is
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architecture logic of plasma is
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_data_r : std_logic_vector(31 downto 0);
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signal mem_data_r : std_logic_vector(31 downto 0);
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signal mem_data_w : std_logic_vector(31 downto 0);
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signal mem_data_w : std_logic_vector(31 downto 0);
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signal mem_byte_sel : std_logic_vector(3 downto 0);
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signal mem_byte_sel : std_logic_vector(3 downto 0);
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signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause_uart : std_logic;
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signal mem_pause_uart : std_logic;
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signal uart_sel : std_logic;
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signal uart_sel : std_logic;
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begin --architecture
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begin --architecture
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mem_pause <= mem_pause_in or mem_pause_uart;
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and mem_byte_sel /= "0000" else
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mem_byte_sel /= "0000" else '0';
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'0';
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mem_data <= mem_data_r;
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mem_data <= mem_data_r;
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mem_pause <= (mem_pause_in and not uart_sel) or mem_pause_uart;
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u1_cpu: mlite_cpu
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u1_cpu: mlite_cpu
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generic map (memory_type => memory_type)
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generic map (memory_type => memory_type)
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PORT MAP (
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PORT MAP (
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clk => clk_in,
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clk => clk_in,
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reset_in => reset_in,
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reset_in => reset_in,
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intr_in => intr_in,
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intr_in => intr_in,
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mem_address => mem_address,
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mem_address => mem_address,
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mem_data_w => mem_data_w,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data_r,
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mem_data_r => mem_data_r,
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mem_byte_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
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mem_write => mem_write,
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mem_pause => mem_pause);
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mem_pause => mem_pause);
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u2_ram: ram
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u2_ram: ram
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generic map (memory_type => memory_type)
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generic map (memory_type => memory_type)
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PORT MAP (
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PORT MAP (
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clk => clk_in,
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clk => clk_in,
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mem_byte_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
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mem_write => mem_write,
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mem_address => mem_address,
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mem_address => mem_address,
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mem_data_w => mem_data_w,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data_r);
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mem_data_r => mem_data_r);
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u3_uart: uart
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u3_uart: uart
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generic map (log_file => log_file)
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generic map (log_file => log_file)
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port map(
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port map(
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clk => clk_in,
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clk => clk_in,
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reset => reset_in,
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reset => reset_in,
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uart_sel => uart_sel,
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uart_sel => uart_sel,
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data => mem_data_w(7 downto 0),
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data => mem_data_w(7 downto 0),
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uart_write => uart_write,
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uart_write => uart_write,
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uart_read => uart_read,
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uart_read => uart_read,
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pause => mem_pause_uart);
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pause => mem_pause_uart);
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mem_address_out <= mem_address;
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mem_address_out <= mem_address;
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mem_byte_sel_out <= mem_byte_sel;
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mem_byte_sel_out <= mem_byte_sel;
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mem_write_out <= mem_write;
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mem_write_out <= mem_write;
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end; --architecture logic
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end; --architecture logic
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