---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
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-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/6/02
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-- DATE CREATED: 6/6/02
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-- FILENAME: plasma_if.vhd
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-- FILENAME: plasma_if.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity divides the clock by two and interfaces to the
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-- This entity divides the clock by two and interfaces to the
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-- Altera EP20K200EFC484-2X FPGA board.
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-- Altera EP20K200EFC484-2X FPGA board.
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-- Xilinx Spartan-3 XC3S200FT256-4 FPGA.
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-- Xilinx Spartan-3 XC3S200FT256-4 FPGA.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--use work.mlite_pack.all;
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--use work.mlite_pack.all;
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entity plasma_if is
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entity plasma_if is
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port(clk_in : in std_logic;
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port(clk_in : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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ram_address : out std_logic_vector(31 downto 2);
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ram_address : out std_logic_vector(31 downto 2);
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ram_data : inout std_logic_vector(31 downto 0);
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ram_data : inout std_logic_vector(31 downto 0);
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ram_ce1_n : out std_logic;
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ram_ce1_n : out std_logic;
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ram_ub1_n : out std_logic;
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ram_ub1_n : out std_logic;
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ram_lb1_n : out std_logic;
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ram_lb1_n : out std_logic;
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ram_ce2_n : out std_logic;
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ram_ce2_n : out std_logic;
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ram_ub2_n : out std_logic;
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ram_ub2_n : out std_logic;
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ram_lb2_n : out std_logic;
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ram_lb2_n : out std_logic;
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ram_we_n : out std_logic;
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ram_we_n : out std_logic;
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ram_oe_n : out std_logic;
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ram_oe_n : out std_logic;
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gpio0_out : out std_logic_vector(31 downto 0);
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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gpioA_in : in std_logic_vector(31 downto 0));
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end; --entity plasma_if
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end; --entity plasma_if
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architecture logic of plasma_if is
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architecture logic of plasma_if is
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component plasma
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component plasma
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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log_file : string := "UNUSED");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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address : out std_logic_vector(31 downto 2);
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address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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mem_pause_in : in std_logic;
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mem_pause_in : in std_logic;
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gpio0_out : out std_logic_vector(31 downto 0);
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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gpioA_in : in std_logic_vector(31 downto 0));
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end component; --plasma
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end component; --plasma
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signal clk_reg : std_logic;
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signal clk_reg : std_logic;
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signal we_n_next : std_logic;
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signal we_n_next : std_logic;
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signal we_n_reg : std_logic;
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signal we_n_reg : std_logic;
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signal mem_address : std_logic_vector(31 downto 2);
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signal mem_address : std_logic_vector(31 downto 2);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal mem_pause_in : std_logic;
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signal mem_pause_in : std_logic;
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begin --architecture
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begin --architecture
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--Divide 50 MHz clock by two
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--Divide 50 MHz clock by two
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clk_div: process(reset, clk_in, clk_reg, we_n_next)
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clk_div: process(reset, clk_in, clk_reg, we_n_next)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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clk_reg <= '0';
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clk_reg <= '0';
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elsif rising_edge(clk_in) then
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elsif rising_edge(clk_in) then
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clk_reg <= not clk_reg;
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clk_reg <= not clk_reg;
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end if;
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end if;
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if reset = '1' then
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if reset = '1' then
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we_n_reg <= '1';
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we_n_reg <= '1';
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data_reg <= (others => '0');
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data_reg <= (others => '0');
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elsif falling_edge(clk_in) then
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elsif falling_edge(clk_in) then
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we_n_reg <= we_n_next or not clk_reg;
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we_n_reg <= we_n_next or not clk_reg;
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data_reg <= ram_data;
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data_reg <= ram_data;
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end if;
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end if;
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end process; --clk_div
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end process; --clk_div
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mem_pause_in <= '0';
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mem_pause_in <= '0';
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ram_address <= mem_address(31 downto 2);
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ram_address <= mem_address(31 downto 2);
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ram_we_n <= we_n_reg;
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ram_we_n <= we_n_reg;
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--For Xilinx Spartan-3 Starter Kit
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--For Xilinx Spartan-3 Starter Kit
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ram_control:
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ram_control:
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process(clk_reg, mem_address, byte_we, data_write)
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process(clk_reg, mem_address, byte_we, data_write)
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begin
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begin
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if mem_address(30 downto 28) = "001" then --RAM
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if mem_address(30 downto 28) = "001" then --RAM
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ram_ce1_n <= '0';
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ram_ce1_n <= '0';
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ram_ce2_n <= '0';
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ram_ce2_n <= '0';
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if byte_we = "0000" then --read
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if byte_we = "0000" then --read
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ram_data <= (others => 'Z');
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ram_data <= (others => 'Z');
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ram_ub1_n <= '0';
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ram_ub1_n <= '0';
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ram_lb1_n <= '0';
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ram_lb1_n <= '0';
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ram_ub2_n <= '0';
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ram_ub2_n <= '0';
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ram_lb2_n <= '0';
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ram_lb2_n <= '0';
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we_n_next <= '1';
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we_n_next <= '1';
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ram_oe_n <= '0';
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ram_oe_n <= '0';
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else --write
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else --write
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if clk_reg = '1' then
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if clk_reg = '1' then
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ram_data <= (others => 'Z');
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ram_data <= (others => 'Z');
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else
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else
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ram_data <= data_write;
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ram_data <= data_write;
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end if;
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end if;
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ram_ub1_n <= not byte_we(3);
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ram_ub1_n <= not byte_we(3);
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ram_lb1_n <= not byte_we(2);
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ram_lb1_n <= not byte_we(2);
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ram_ub2_n <= not byte_we(1);
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ram_ub2_n <= not byte_we(1);
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ram_lb2_n <= not byte_we(0);
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ram_lb2_n <= not byte_we(0);
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we_n_next <= '0';
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we_n_next <= '0';
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ram_oe_n <= '1';
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ram_oe_n <= '1';
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end if;
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end if;
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else
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else
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ram_data <= (others => 'Z');
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ram_data <= (others => 'Z');
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ram_ce1_n <= '1';
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ram_ce1_n <= '1';
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ram_ub1_n <= '1';
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ram_ub1_n <= '1';
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ram_lb1_n <= '1';
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ram_lb1_n <= '1';
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ram_ce2_n <= '1';
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ram_ce2_n <= '1';
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ram_ub2_n <= '1';
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ram_ub2_n <= '1';
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ram_lb2_n <= '1';
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ram_lb2_n <= '1';
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we_n_next <= '1';
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we_n_next <= '1';
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ram_oe_n <= '1';
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ram_oe_n <= '1';
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end if;
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end if;
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end process; --ram_control
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end process; --ram_control
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u1_plama: plasma
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u1_plama: plasma
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generic map (memory_type => "XILINX_16X",
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generic map (memory_type => "XILINX_16X",
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log_file => "UNUSED")
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log_file => "UNUSED")
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PORT MAP (
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PORT MAP (
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clk => clk_reg,
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clk => clk_reg,
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reset => reset,
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reset => reset,
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uart_write => uart_write,
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uart_write => uart_write,
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uart_read => uart_read,
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uart_read => uart_read,
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address => mem_address,
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address => mem_address,
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byte_we => byte_we,
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byte_we => byte_we,
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data_write => data_write,
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data_write => data_write,
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data_read => data_reg,
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data_read => data_reg,
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mem_pause_in => mem_pause_in,
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mem_pause_in => mem_pause_in,
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gpio0_out => gpio0_out,
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gpio0_out => gpio0_out,
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gpioA_in => gpioA_in);
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gpioA_in => gpioA_in);
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end; --architecture logic
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end; --architecture logic
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