---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Random Access Memory
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-- TITLE: Random Access Memory
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- DATE CREATED: 4/21/01
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-- FILENAME: ram.vhd
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-- FILENAME: ram.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the RAM, reads the executable from either "code.txt",
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-- Implements the RAM, reads the executable from either "code.txt",
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-- or for Altera "code[0-3].hex".
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-- or for Altera "code[0-3].hex".
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-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity ram is
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entity ram is
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generic(memory_type : string := "DEFAULT");
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generic(memory_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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write_byte_enable : in std_logic_vector(3 downto 0);
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write_byte_enable : in std_logic_vector(3 downto 0);
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address : in std_logic_vector(31 downto 2);
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address : in std_logic_vector(31 downto 2);
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data_write : in std_logic_vector(31 downto 0);
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0));
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data_read : out std_logic_vector(31 downto 0));
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end; --entity ram
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end; --entity ram
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architecture logic of ram is
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architecture logic of ram is
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constant ADDRESS_WIDTH : natural := 13;
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constant ADDRESS_WIDTH : natural := 13;
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begin
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begin
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generic_ram:
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generic_ram:
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if memory_type /= "ALTERA_LPM" generate
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if memory_type /= "ALTERA_LPM" generate
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begin
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begin
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--Simulate a synchronous RAM
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--Simulate a synchronous RAM
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ram_proc: process(clk, enable, write_byte_enable,
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ram_proc: process(clk, enable, write_byte_enable,
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address, data_write) --mem_write, mem_sel
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address, data_write) --mem_write, mem_sel
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variable mem_size : natural := 2 ** ADDRESS_WIDTH;
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variable mem_size : natural := 2 ** ADDRESS_WIDTH;
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variable data : std_logic_vector(31 downto 0);
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variable data : std_logic_vector(31 downto 0);
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subtype word is std_logic_vector(data_write'length-1 downto 0);
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subtype word is std_logic_vector(data_write'length-1 downto 0);
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type storage_array is
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type storage_array is
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array(natural range 0 to mem_size/4 - 1) of word;
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array(natural range 0 to mem_size/4 - 1) of word;
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variable storage : storage_array;
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variable storage : storage_array;
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variable index : natural := 0;
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variable index : natural := 0;
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file load_file : text open read_mode is "code.txt";
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file load_file : text open read_mode is "code.txt";
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variable hex_file_line : line;
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variable hex_file_line : line;
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begin
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begin
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--Load in the ram executable image
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--Load in the ram executable image
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if index = 0 then
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if index = 0 then
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while not endfile(load_file) loop
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while not endfile(load_file) loop
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--The following two lines had to be commented out for synthesis
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--The following two lines had to be commented out for synthesis
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readline(load_file, hex_file_line);
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readline(load_file, hex_file_line);
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hread(hex_file_line, data);
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hread(hex_file_line, data);
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storage(index) := data;
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storage(index) := data;
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index := index + 1;
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index := index + 1;
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end loop;
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end loop;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
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index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
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data := storage(index);
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data := storage(index);
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if enable = '1' then
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if enable = '1' then
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if write_byte_enable(0) = '1' then
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if write_byte_enable(0) = '1' then
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data(7 downto 0) := data_write(7 downto 0);
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data(7 downto 0) := data_write(7 downto 0);
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end if;
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end if;
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if write_byte_enable(1) = '1' then
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if write_byte_enable(1) = '1' then
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data(15 downto 8) := data_write(15 downto 8);
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data(15 downto 8) := data_write(15 downto 8);
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end if;
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end if;
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if write_byte_enable(2) = '1' then
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if write_byte_enable(2) = '1' then
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data(23 downto 16) := data_write(23 downto 16);
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data(23 downto 16) := data_write(23 downto 16);
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end if;
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end if;
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if write_byte_enable(3) = '1' then
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if write_byte_enable(3) = '1' then
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data(31 downto 24) := data_write(31 downto 24);
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data(31 downto 24) := data_write(31 downto 24);
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end if;
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end if;
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end if;
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end if;
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if write_byte_enable /= "0000" then
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if write_byte_enable /= "0000" then
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storage(index) := data;
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storage(index) := data;
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end if;
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end if;
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end if;
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end if;
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data_read <= data;
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data_read <= data;
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end process;
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end process;
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end generate; --generic_ram
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end generate; --generic_ram
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altera_ram:
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altera_ram:
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if memory_type = "ALTERA_LPM" generate
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if memory_type = "ALTERA_LPM" generate
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signal byte_we : std_logic_vector(3 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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begin
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begin
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byte_we <= write_byte_enable when enable = '1' else "0000";
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byte_we <= write_byte_enable when enable = '1' else "0000";
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lpm_ram_io_component0 : lpm_ram_dq
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lpm_ram_io_component0 : lpm_ram_dq
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GENERIC MAP (
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GENERIC MAP (
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intended_device_family => "UNUSED",
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_width => 8,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_indata => "REGISTERED",
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lpm_indata => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code0.hex",
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lpm_file => "code0.hex",
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use_eab => "ON",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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PORT MAP (
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data => data_write(31 downto 24),
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data => data_write(31 downto 24),
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address => address(ADDRESS_WIDTH-1 downto 2),
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address => address(ADDRESS_WIDTH-1 downto 2),
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inclock => clk,
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inclock => clk,
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we => byte_we(3),
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we => byte_we(3),
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q => data_read(31 downto 24));
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q => data_read(31 downto 24));
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lpm_ram_io_component1 : lpm_ram_dq
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lpm_ram_io_component1 : lpm_ram_dq
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GENERIC MAP (
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GENERIC MAP (
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intended_device_family => "UNUSED",
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_width => 8,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_indata => "REGISTERED",
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lpm_indata => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code1.hex",
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lpm_file => "code1.hex",
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use_eab => "ON",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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PORT MAP (
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data => data_write(23 downto 16),
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data => data_write(23 downto 16),
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address => address(ADDRESS_WIDTH-1 downto 2),
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address => address(ADDRESS_WIDTH-1 downto 2),
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inclock => clk,
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inclock => clk,
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we => byte_we(2),
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we => byte_we(2),
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q => data_read(23 downto 16));
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q => data_read(23 downto 16));
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lpm_ram_io_component2 : lpm_ram_dq
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lpm_ram_io_component2 : lpm_ram_dq
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GENERIC MAP (
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GENERIC MAP (
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intended_device_family => "UNUSED",
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_width => 8,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_indata => "REGISTERED",
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lpm_indata => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code2.hex",
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lpm_file => "code2.hex",
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use_eab => "ON",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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PORT MAP (
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data => data_write(15 downto 8),
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data => data_write(15 downto 8),
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address => address(ADDRESS_WIDTH-1 downto 2),
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address => address(ADDRESS_WIDTH-1 downto 2),
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inclock => clk,
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inclock => clk,
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we => byte_we(1),
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we => byte_we(1),
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q => data_read(15 downto 8));
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q => data_read(15 downto 8));
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lpm_ram_io_component3 : lpm_ram_dq
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lpm_ram_io_component3 : lpm_ram_dq
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GENERIC MAP (
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GENERIC MAP (
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intended_device_family => "UNUSED",
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_width => 8,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_widthad => ADDRESS_WIDTH-2,
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lpm_indata => "REGISTERED",
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lpm_indata => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_address_control => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code3.hex",
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lpm_file => "code3.hex",
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use_eab => "ON",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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PORT MAP (
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data => data_write(7 downto 0),
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data => data_write(7 downto 0),
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address => address(ADDRESS_WIDTH-1 downto 2),
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address => address(ADDRESS_WIDTH-1 downto 2),
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inclock => clk,
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inclock => clk,
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we => byte_we(0),
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we => byte_we(0),
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q => data_read(7 downto 0));
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q => data_read(7 downto 0));
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end generate; --altera_ram
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end generate; --altera_ram
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--For XILINX see ram_xilinx.vhd
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--For XILINX see ram_xilinx.vhd
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end; --architecture logic
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end; --architecture logic
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