---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Test Bench
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-- TITLE: Test Bench
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- DATE CREATED: 4/21/01
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-- FILENAME: tbench.vhd
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-- FILENAME: tbench.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity provides a test bench for testing the Plasma CPU core.
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-- This entity provides a test bench for testing the Plasma CPU core.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity tbench is
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entity tbench is
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end; --entity tbench
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end; --entity tbench
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architecture logic of tbench is
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architecture logic of tbench is
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constant memory_type : string :=
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constant memory_type : string :=
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"GENERIC";
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"GENERIC";
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-- "ALTERA";
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-- "ALTERA";
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-- "XILINX";
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-- "XILINX";
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constant log_file : string :=
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constant log_file : string :=
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-- "UNUSED"
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-- "UNUSED"
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"output.txt";
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"output.txt";
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signal clk : std_logic := '1';
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signal clk : std_logic := '1';
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_data : std_logic_vector(31 downto 0);
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signal mem_data : std_logic_vector(31 downto 0);
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signal mem_pause : std_logic := '0';
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signal mem_pause : std_logic := '0';
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signal mem_byte_sel: std_logic_vector(3 downto 0);
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signal mem_byte_sel: std_logic_vector(3 downto 0);
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signal uart_read : std_logic;
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signal uart_read : std_logic;
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signal uart_write : std_logic;
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signal uart_write : std_logic;
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begin --architecture
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begin --architecture
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clk <= not clk after 50 ns;
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clk <= not clk after 50 ns;
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reset <= '0' after 500 ns;
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reset <= '0' after 500 ns;
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uart_read <= '0';
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--Uncomment the line below to test interrupts
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--Uncomment the line below to test interrupts
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-- interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;
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-- interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;
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--Uncomment the line below to test mem_pause
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--Uncomment the line below to test mem_pause
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-- mem_pause <= '1' after 100 ns when mem_pause = '0' else '0' after 100 ns;
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-- mem_pause <= '1' after 100 ns when mem_pause = '0' else '0' after 100 ns;
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u1: plasma
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u1: plasma
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generic map (memory_type => memory_type,
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generic map (memory_type => memory_type,
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log_file => log_file)
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log_file => log_file)
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PORT MAP (
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PORT MAP (
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clk_in => clk,
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clk_in => clk,
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reset_in => reset,
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reset_in => reset,
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intr_in => interrupt,
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intr_in => interrupt,
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uart_read => uart_read,
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uart_read => uart_read,
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uart_write => uart_write,
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uart_write => uart_write,
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mem_address_out => mem_address,
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mem_address_out => mem_address,
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mem_data => mem_data,
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mem_data => mem_data,
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mem_byte_sel_out => mem_byte_sel,
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mem_byte_sel_out => mem_byte_sel,
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mem_write_out => mem_write,
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mem_write_out => mem_write,
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mem_pause_in => mem_pause);
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mem_pause_in => mem_pause);
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end; --architecture logic
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end; --architecture logic
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