---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Test Bench
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-- TITLE: Test Bench
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- DATE CREATED: 4/21/01
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-- FILENAME: tbench.vhd
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-- FILENAME: tbench.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity provides a test bench for testing the Plasma CPU core.
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-- This entity provides a test bench for testing the Plasma CPU core.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity tbench is
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entity tbench is
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end; --entity tbench
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end; --entity tbench
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architecture logic of tbench is
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architecture logic of tbench is
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constant memory_type : string :=
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constant memory_type : string :=
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"TRI_PORT_X";
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"TRI_PORT_X";
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-- "DUAL_PORT_";
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-- "DUAL_PORT_";
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-- "ALTERA_LPM";
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-- "ALTERA_LPM";
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-- "XILINX_16X";
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-- "XILINX_16X";
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constant log_file : string :=
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constant log_file : string :=
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-- "UNUSED";
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-- "UNUSED";
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"output.txt";
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"output.txt";
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signal clk : std_logic := '1';
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signal clk : std_logic := '1';
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal address : std_logic_vector(31 downto 2);
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signal address : std_logic_vector(31 downto 2);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal pause1 : std_logic := '0';
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signal pause1 : std_logic := '0';
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signal pause2 : std_logic := '0';
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signal pause2 : std_logic := '0';
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signal pause : std_logic;
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signal pause : std_logic;
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signal no_ddr_start: std_logic;
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signal no_ddr_start: std_logic;
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signal no_ddr_stop : std_logic;
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signal no_ddr_stop : std_logic;
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signal byte_we : std_logic_vector(3 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal uart_write : std_logic;
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signal uart_write : std_logic;
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signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
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signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
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begin --architecture
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begin --architecture
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--Uncomment the line below to test interrupts
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--Uncomment the line below to test interrupts
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interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
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interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
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clk <= not clk after 50 ns;
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clk <= not clk after 50 ns;
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reset <= '0' after 500 ns;
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reset <= '0' after 500 ns;
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pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
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pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
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pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
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pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
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pause <= pause1 or pause2;
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pause <= pause1 or pause2;
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gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
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gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
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gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
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gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
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gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
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gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
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gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
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gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
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u1_plasma: plasma
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u1_plasma: plasma
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generic map (memory_type => memory_type,
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generic map (memory_type => memory_type,
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ethernet => '1',
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ethernet => '1',
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use_cache => '1',
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use_cache => '1',
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log_file => log_file)
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log_file => log_file)
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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uart_read => uart_write,
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uart_read => uart_write,
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uart_write => uart_write,
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uart_write => uart_write,
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address => address,
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address => address,
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byte_we => byte_we,
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byte_we => byte_we,
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data_write => data_write,
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data_write => data_write,
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data_read => data_read,
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data_read => data_read,
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mem_pause_in => pause,
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mem_pause_in => pause,
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no_ddr_start => no_ddr_start,
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no_ddr_start => no_ddr_start,
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no_ddr_stop => no_ddr_stop,
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no_ddr_stop => no_ddr_stop,
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gpio0_out => open,
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gpio0_out => open,
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gpioA_in => gpioA_in);
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gpioA_in => gpioA_in);
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dram_proc: process(clk, address, byte_we, data_write, pause)
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dram_proc: process(clk, address, byte_we, data_write, pause)
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constant ADDRESS_WIDTH : natural := 16;
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constant ADDRESS_WIDTH : natural := 16;
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type storage_array is
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type storage_array is
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array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
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array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
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std_logic_vector(31 downto 0);
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std_logic_vector(31 downto 0);
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variable storage : storage_array;
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variable storage : storage_array;
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variable data : std_logic_vector(31 downto 0);
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variable data : std_logic_vector(31 downto 0);
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variable index : natural := 0;
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variable index : natural := 0;
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begin
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begin
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index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
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index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
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data := storage(index);
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data := storage(index);
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if byte_we(0) = '1' then
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if byte_we(0) = '1' then
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data(7 downto 0) := data_write(7 downto 0);
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data(7 downto 0) := data_write(7 downto 0);
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end if;
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end if;
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if byte_we(1) = '1' then
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if byte_we(1) = '1' then
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data(15 downto 8) := data_write(15 downto 8);
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data(15 downto 8) := data_write(15 downto 8);
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end if;
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end if;
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if byte_we(2) = '1' then
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if byte_we(2) = '1' then
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data(23 downto 16) := data_write(23 downto 16);
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data(23 downto 16) := data_write(23 downto 16);
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end if;
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end if;
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if byte_we(3) = '1' then
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if byte_we(3) = '1' then
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data(31 downto 24) := data_write(31 downto 24);
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data(31 downto 24) := data_write(31 downto 24);
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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if address(30 downto 28) = "001" and byte_we /= "0000" then
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if address(30 downto 28) = "001" and byte_we /= "0000" then
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storage(index) := data;
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storage(index) := data;
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end if;
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end if;
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end if;
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end if;
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if pause = '0' then
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if pause = '0' then
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data_read <= data;
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data_read <= data;
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end if;
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end if;
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end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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