-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Montgomery modular multiplier and exponentiator ----
|
---- Montgomery modular multiplier and exponentiator ----
|
---- ----
|
---- ----
|
---- This file is part of the Montgomery modular multiplier ----
|
---- This file is part of the Montgomery modular multiplier ----
|
---- and exponentiator project ----
|
---- and exponentiator project ----
|
---- http://opencores.org/project,mod_mult_exp ----
|
---- http://opencores.org/project,mod_mult_exp ----
|
---- ----
|
---- ----
|
---- Description: ----
|
---- Description: ----
|
---- Montgomery modular exponentiator main module. It combines ----
|
---- Montgomery modular exponentiator main module. It combines ----
|
---- all subomponents. It takes four numbers as the input: ----
|
---- all subcomponents. It takes four numbers as the input: ----
|
---- base, power, modulus and Montgomery residuum ----
|
---- base, power, modulus and Montgomery residuum ----
|
---- (2^(2*word_length) mod N) and results the modular ----
|
---- (2^(2*word_length) mod N) and results the modular ----
|
---- exponentiation A^B mod M. ----
|
---- exponentiation A^B mod M. ----
|
---- In fact input data are read through one input controlled by ----
|
---- In fact input data are read through one input controlled by ----
|
---- the ctrl input. ----
|
---- the ctrl input. ----
|
---- To Do: ----
|
---- To Do: ----
|
---- ----
|
---- ----
|
---- Author(s): ----
|
---- Author(s): ----
|
---- - Krzysztof Gajewski, gajos@opencores.org ----
|
---- - Krzysztof Gajewski, gajos@opencores.org ----
|
---- k.gajewski@gmail.com ----
|
---- k.gajewski@gmail.com ----
|
---- ----
|
---- ----
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- ----
|
---- ----
|
---- This source file is free software; you can redistribute it ----
|
---- This source file is free software; you can redistribute it ----
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
|
---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
|
---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- ----
|
---- ----
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use work.properties.ALL;
|
use work.properties.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
-- Uncomment the following library declaration if using
|
-- Uncomment the following library declaration if using
|
-- arithmetic functions with Signed or Unsigned values
|
-- arithmetic functions with Signed or Unsigned values
|
--use IEEE.NUMERIC_STD.ALL;
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
-- Uncomment the following library declaration if instantiating
|
-- Uncomment the following library declaration if instantiating
|
-- any Xilinx primitives in this code.
|
-- any Xilinx primitives in this code.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity ModExp is
|
entity ModExp is
|
generic (
|
generic (
|
word_size : integer := WORD_LENGTH;
|
word_size : integer := WORD_LENGTH;
|
word_binary : integer := WORD_INTEGER
|
word_binary : integer := WORD_INTEGER
|
);
|
);
|
Port (
|
Port (
|
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
ctrl : in STD_LOGIC_VECTOR(2 downto 0);
|
ctrl : in STD_LOGIC_VECTOR(2 downto 0);
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
data_in_ready : in STD_LOGIC;
|
data_in_ready : in STD_LOGIC;
|
ready : out STD_LOGIC;
|
ready : out STD_LOGIC;
|
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0)
|
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0)
|
);
|
);
|
end ModExp;
|
end ModExp;
|
|
|
architecture Behavioral of ModExp is
|
architecture Behavioral of ModExp is
|
|
|
-- Montgomery modular multiplier component
|
-- Montgomery modular multiplier component
|
component ModularMultiplierIterative is
|
component ModularMultiplierIterative is
|
generic (
|
generic (
|
word_size : integer := WORD_LENGTH
|
word_size : integer := WORD_LENGTH
|
);
|
);
|
port (
|
port (
|
A : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplicand
|
A : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplicand
|
B : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplier
|
B : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- multiplier
|
M : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- modulus
|
M : in STD_LOGIC_VECTOR(word_size - 1 downto 0); -- modulus
|
start : in STD_LOGIC;
|
start : in STD_LOGIC;
|
product : out STD_LOGIC_VECTOR(word_size - 1 downto 0); -- product
|
product : out STD_LOGIC_VECTOR(word_size - 1 downto 0); -- product
|
ready : out STD_LOGIC;
|
ready : out STD_LOGIC;
|
clk : in STD_LOGIC
|
clk : in STD_LOGIC
|
);
|
);
|
end component ModularMultiplierIterative;
|
end component ModularMultiplierIterative;
|
|
|
-- Block memory component generated through ISE
|
-- Block memory component generated through ISE
|
-- It is used like multiple cell register
|
-- It is used like multiple cell register
|
COMPONENT blockMemory
|
COMPONENT blockMemory
|
PORT (
|
PORT (
|
clka : in STD_LOGIC;
|
clka : in STD_LOGIC;
|
rsta : in STD_LOGIC;
|
rsta : in STD_LOGIC;
|
wea : in STD_LOGIC_VECTOR(0 DOWNTO 0);
|
wea : in STD_LOGIC_VECTOR(0 DOWNTO 0);
|
addra : in STD_LOGIC_VECTOR(3 DOWNTO 0);
|
addra : in STD_LOGIC_VECTOR(3 DOWNTO 0);
|
dina : in STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0);
|
dina : in STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0);
|
douta : out STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0)
|
douta : out STD_LOGIC_VECTOR(word_size - 1 DOWNTO 0)
|
);
|
);
|
END COMPONENT;
|
END COMPONENT;
|
|
|
-- Register
|
-- Register
|
component Reg is
|
component Reg is
|
generic(
|
generic(
|
word_size : integer := WORD_LENGTH
|
word_size : integer := WORD_LENGTH
|
);
|
);
|
port(
|
port(
|
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
input : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
output : out STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
enable : in STD_LOGIC;
|
enable : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
reset : in STD_LOGIC
|
reset : in STD_LOGIC
|
);
|
);
|
end component Reg;
|
end component Reg;
|
|
|
-- Multiplexer
|
-- Multiplexer
|
component MontMult4inMux is
|
component MontMult4inMux is
|
generic (
|
generic (
|
word_size : integer := WORD_LENGTH - 1
|
word_size : integer := WORD_LENGTH - 1
|
);
|
);
|
port (
|
port (
|
ctrl : in STD_LOGIC_VECTOR(1 downto 0);
|
ctrl : in STD_LOGIC_VECTOR(1 downto 0);
|
zero : in STD_LOGIC_VECTOR(word_size downto 0);
|
zero : in STD_LOGIC_VECTOR(word_size downto 0);
|
M : in STD_LOGIC_VECTOR(word_size downto 0);
|
M : in STD_LOGIC_VECTOR(word_size downto 0);
|
Y : in STD_LOGIC_VECTOR(word_size downto 0);
|
Y : in STD_LOGIC_VECTOR(word_size downto 0);
|
YplusM : in STD_LOGIC_VECTOR(word_size downto 0);
|
YplusM : in STD_LOGIC_VECTOR(word_size downto 0);
|
output : out STD_LOGIC_VECTOR(word_size downto 0)
|
output : out STD_LOGIC_VECTOR(word_size downto 0)
|
);
|
);
|
end component MontMult4inMux;
|
end component MontMult4inMux;
|
|
|
-- State machine
|
-- State machine
|
component ModExpSM is
|
component ModExpSM is
|
generic(
|
generic(
|
word_size : integer := WORD_LENGTH;
|
word_size : integer := WORD_LENGTH;
|
word_binary : integer := WORD_INTEGER
|
word_binary : integer := WORD_INTEGER
|
);
|
);
|
port (
|
port (
|
data_in_ready : in STD_LOGIC;
|
data_in_ready : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
exp_ctrl : in STD_LOGIC_VECTOR(2 downto 0);
|
exp_ctrl : in STD_LOGIC_VECTOR(2 downto 0);
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
in_mux_control : out STD_LOGIC_VECTOR(1 downto 0);
|
in_mux_control : out STD_LOGIC_VECTOR(1 downto 0);
|
-- finalizer end status
|
-- finalizer end status
|
ready : out STD_LOGIC;
|
ready : out STD_LOGIC;
|
-- control for multiplier
|
-- control for multiplier
|
modMultStart : out STD_LOGIC;
|
modMultStart : out STD_LOGIC;
|
modMultReady : in STD_LOGIC;
|
modMultReady : in STD_LOGIC;
|
-- control for memory and registers
|
-- control for memory and registers
|
addr_dataA : out STD_LOGIC_VECTOR(3 downto 0);
|
addr_dataA : out STD_LOGIC_VECTOR(3 downto 0);
|
addr_dataB : out STD_LOGIC_VECTOR(3 downto 0);
|
addr_dataB : out STD_LOGIC_VECTOR(3 downto 0);
|
regData_EnA : out STD_LOGIC_VECTOR(0 downto 0);
|
regData_EnA : out STD_LOGIC_VECTOR(0 downto 0);
|
regData_EnB : out STD_LOGIC_VECTOR(0 downto 0);
|
regData_EnB : out STD_LOGIC_VECTOR(0 downto 0);
|
regData_EnC : out STD_LOGIC;
|
regData_EnC : out STD_LOGIC;
|
regData_EnExponent : out STD_LOGIC;
|
regData_EnExponent : out STD_LOGIC;
|
ExponentData : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
ExponentData : in STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
memory_reset : out STD_LOGIC
|
memory_reset : out STD_LOGIC
|
);
|
);
|
end component ModExpSM;
|
end component ModExpSM;
|
|
|
-- data registers signals
|
-- data registers signals
|
signal addr_dataA : STD_LOGIC_VECTOR(3 downto 0);
|
signal addr_dataA : STD_LOGIC_VECTOR(3 downto 0);
|
signal addr_dataB : STD_LOGIC_VECTOR(3 downto 0);
|
signal addr_dataB : STD_LOGIC_VECTOR(3 downto 0);
|
|
|
signal memDataLoadA : STD_LOGIC_VECTOR(0 downto 0);
|
signal memDataLoadA : STD_LOGIC_VECTOR(0 downto 0);
|
signal memDataLoadB : STD_LOGIC_VECTOR(0 downto 0);
|
signal memDataLoadB : STD_LOGIC_VECTOR(0 downto 0);
|
signal memDataLoadC : STD_LOGIC;
|
signal memDataLoadC : STD_LOGIC;
|
signal memDataLoadExponent : STD_LOGIC;
|
signal memDataLoadExponent : STD_LOGIC;
|
|
|
signal memDataA : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataA : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataB : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataB : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataC : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataC : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataExponent : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memDataExponent : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memoryIn : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal memoryIn : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
|
|
signal in_mux_control : STD_LOGIC_VECTOR(1 downto 0);
|
signal in_mux_control : STD_LOGIC_VECTOR(1 downto 0);
|
|
|
-- signal for multiplier
|
-- signal for multiplier
|
signal multStart : STD_LOGIC;
|
signal multStart : STD_LOGIC;
|
signal multReady : STD_LOGIC;
|
signal multReady : STD_LOGIC;
|
signal modMultToBuffer : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
signal modMultToBuffer : STD_LOGIC_VECTOR(word_size - 1 downto 0);
|
|
|
signal zero : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (others => '0');
|
signal zero : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (others => '0');
|
signal one : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (0 => '1', others => '0');
|
signal one : STD_LOGIC_VECTOR(word_size - 1 downto 0) := (0 => '1', others => '0');
|
|
|
signal memory_reset : STD_LOGIC;
|
signal memory_reset : STD_LOGIC;
|
|
|
begin
|
begin
|
-- connections between components
|
-- connections between components
|
zero <= (others => '0');
|
zero <= (others => '0');
|
one <= (0 => '1', others => '0');
|
one <= (0 => '1', others => '0');
|
|
|
-- Montgomery modular multiplier component
|
-- Montgomery modular multiplier component
|
modMult : ModularMultiplierIterative
|
modMult : ModularMultiplierIterative
|
port map (
|
port map (
|
A => memDataA,
|
A => memDataA,
|
B => memDataB,
|
B => memDataB,
|
M => memDataC,
|
M => memDataC,
|
start => multStart,
|
start => multStart,
|
product => modMultToBuffer,
|
product => modMultToBuffer,
|
ready => multReady,
|
ready => multReady,
|
clk => clk
|
clk => clk
|
);
|
);
|
|
|
-- Multiplexer
|
-- Multiplexer
|
mux : MontMult4inMux
|
mux : MontMult4inMux
|
port map (
|
port map (
|
ctrl => in_mux_control,
|
ctrl => in_mux_control,
|
zero => zero,
|
zero => zero,
|
M => one,
|
M => one,
|
Y => modMultToBuffer,
|
Y => modMultToBuffer,
|
YplusM => input,
|
YplusM => input,
|
output => memoryIn
|
output => memoryIn
|
);
|
);
|
|
|
-- Block memory for the first input of the multiplier
|
-- Block memory for the first input of the multiplier
|
memoryA : blockMemory
|
memoryA : blockMemory
|
port map (
|
port map (
|
clka => clk,
|
clka => clk,
|
rsta => memory_reset,
|
rsta => memory_reset,
|
wea => memDataLoadA,
|
wea => memDataLoadA,
|
addra => addr_dataA,
|
addra => addr_dataA,
|
dina => memoryIn,
|
dina => memoryIn,
|
douta => memDataA
|
douta => memDataA
|
);
|
);
|
|
|
-- Block memory for the second input of the multiplier
|
-- Block memory for the second input of the multiplier
|
memoryB : blockMemory
|
memoryB : blockMemory
|
port map (
|
port map (
|
clka => clk,
|
clka => clk,
|
rsta => memory_reset,
|
rsta => memory_reset,
|
wea => memDataLoadB,
|
wea => memDataLoadB,
|
addra => addr_dataB,
|
addra => addr_dataB,
|
dina => memoryIn,
|
dina => memoryIn,
|
douta => memDataB
|
douta => memDataB
|
);
|
);
|
|
|
-- Register for the modulus for the multiplier
|
-- Register for the modulus for the multiplier
|
memoryModulus : Reg
|
memoryModulus : Reg
|
port map (
|
port map (
|
input => memoryIn,
|
input => memoryIn,
|
output => memDataC,
|
output => memDataC,
|
enable => memDataLoadC,
|
enable => memDataLoadC,
|
clk => clk,
|
clk => clk,
|
reset => memory_reset
|
reset => memory_reset
|
);
|
);
|
|
|
-- Register for the exponent - it feeds also the state machine for the control of the exponentiation process
|
-- Register for the exponent - it feeds also the state machine for the control of the exponentiation process
|
memoryExponent : Reg
|
memoryExponent : Reg
|
port map (
|
port map (
|
input => memoryIn,
|
input => memoryIn,
|
output => memDataExponent,
|
output => memDataExponent,
|
enable => memDataLoadExponent,
|
enable => memDataLoadExponent,
|
clk => clk,
|
clk => clk,
|
reset => memory_reset
|
reset => memory_reset
|
);
|
);
|
|
|
-- State machine of the Montgomery modular exponentiator
|
-- State machine of the Montgomery modular exponentiator
|
stateMachine : ModExpSM
|
stateMachine : ModExpSM
|
port map(
|
port map(
|
data_in_ready => data_in_ready,
|
data_in_ready => data_in_ready,
|
clk => clk,
|
clk => clk,
|
exp_ctrl => ctrl,
|
exp_ctrl => ctrl,
|
reset => reset,
|
reset => reset,
|
in_mux_control => in_mux_control,
|
in_mux_control => in_mux_control,
|
ready => ready,
|
ready => ready,
|
modMultStart => multStart,
|
modMultStart => multStart,
|
modMultReady => multReady,
|
modMultReady => multReady,
|
addr_dataA => addr_dataA,
|
addr_dataA => addr_dataA,
|
addr_dataB => addr_dataB,
|
addr_dataB => addr_dataB,
|
regData_EnA => memDataLoadA,
|
regData_EnA => memDataLoadA,
|
regData_EnB => memDataLoadB,
|
regData_EnB => memDataLoadB,
|
regData_EnC => memDataLoadC,
|
regData_EnC => memDataLoadC,
|
regData_EnExponent => memDataLoadExponent,
|
regData_EnExponent => memDataLoadExponent,
|
ExponentData => memDataExponent,
|
ExponentData => memDataExponent,
|
memory_reset => memory_reset
|
memory_reset => memory_reset
|
);
|
);
|
|
|
output <= memDataA;
|
output <= memDataA;
|
|
|
|
|