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---- dpram_asym ----
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---- dpram_asym ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- behavorial description of an asymmetric dual port ram ----
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---- behavorial description of an asymmetric dual port ram ----
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---- with one (wrwidth)-bit write port and one 32-bit read ----
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---- with one (wrwidth)-bit write port and one 32-bit read ----
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---- port. Made using the templates of xilinx and altera for ----
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---- port. Made using the templates of xilinx and altera for ----
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---- asymmetric ram. ----
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---- asymmetric ram. ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition
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-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition
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-- option on or contstraint below on) and wrwidth 1,2,4,8,16
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-- option on or contstraint below on) and wrwidth 1,2,4,8,16
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-- xilinx infers ramblocks from a depth of 2 and wrwidth 1,2,4,8,16,32
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-- xilinx infers ramblocks from a depth of 2 and wrwidth 1,2,4,8,16,32
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entity dpram_asym is
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entity dpram_asym is
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generic (
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generic (
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rddepth : integer := 4; -- nr of 32-bit words
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rddepth : integer := 4; -- nr of 32-bit words
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wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
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wrwidth : integer := 2; -- write width, must be smaller than or equal to 32
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device : string := "xilinx" -- device template to use
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device : string := "xilinx" -- device template to use
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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-- write port
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-- write port
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waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
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waddr : in std_logic_vector(log2((rddepth*32)/wrwidth)-1 downto 0);
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we : in std_logic;
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we : in std_logic;
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din : in std_logic_vector(wrwidth-1 downto 0);
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din : in std_logic_vector(wrwidth-1 downto 0);
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-- read port
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-- read port
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raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
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raddr : in std_logic_vector(log2(rddepth)-1 downto 0);
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dout : out std_logic_vector(31 downto 0)
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dout : out std_logic_vector(31 downto 0)
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);
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);
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end dpram_asym;
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end dpram_asym;
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architecture behavorial of dpram_asym is
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architecture behavorial of dpram_asym is
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-- constants
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-- constants
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constant R : natural := 32/wrwidth; -- ratio
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constant R : natural := 32/wrwidth; -- ratio
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constant wrdepth : integer := (rddepth*32)/wrwidth;
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constant wrdepth : integer := (rddepth*32)/wrwidth;
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begin
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begin
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xilinx_device : if device="xilinx" generate
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xilinx_device : if device="xilinx" generate
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-- the memory
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-- the memory
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type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
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type ram_type is array (wrdepth-1 downto 0) of std_logic_vector (wrwidth-1 downto 0);
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signal RAM : ram_type := (others => (others => '0'));
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signal RAM : ram_type := (others => (others => '0'));
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-- xilinx constraint to use blockram resources
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-- xilinx constraint to use blockram resources
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attribute ram_style : string;
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attribute ram_style : string;
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attribute ram_style of ram:signal is "block";
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attribute ram_style of ram:signal is "block";
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begin
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begin
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process (clk)
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process (clk)
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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if (we = '1') then
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if (we = '1') then
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RAM(conv_integer(waddr)) <= din;
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RAM(conv_integer(waddr)) <= din;
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end if;
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end if;
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for i in 0 to R-1 loop
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for i in 0 to R-1 loop
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dout((i+1)*wrwidth-1 downto i*wrwidth)
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dout((i+1)*wrwidth-1 downto i*wrwidth)
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<= RAM(conv_integer(raddr & conv_std_logic_vector(i,log2(R))));
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<= RAM(conv_integer(raddr & conv_std_logic_vector(i,log2(R))));
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end loop;
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end loop;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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altera_device : if device="altera" generate
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altera_device : if device="altera" generate
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-- Use a multidimensional array to model mixed-width
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-- Use a multidimensional array to model mixed-width
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type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
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type word_t is array(R-1 downto 0) of std_logic_vector(wrwidth-1 downto 0);
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type ram_t is array (0 to rddepth-1) of word_t;
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type ram_t is array (0 to rddepth-1) of word_t;
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signal ram : ram_t;
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signal ram : ram_t;
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signal q_local : word_t;
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signal q_local : word_t;
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-- altera constraints:
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-- altera constraints:
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-- for smal depths:
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-- for smal depths:
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-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
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-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
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-- may be left commented.
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-- may be left commented.
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-- uncomment this attribute if that option is off and you know wich primitives should be used.
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-- uncomment this attribute if that option is off and you know wich primitives should be used.
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--attribute ramstyle : string;
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--attribute ramstyle : string;
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--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
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--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
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begin
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begin
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unpack: for i in 0 to R - 1 generate
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unpack: for i in 0 to R - 1 generate
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dout(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
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dout(wrwidth*(i+1) - 1 downto wrwidth*i) <= q_local(i);
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end generate unpack;
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end generate unpack;
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process(clk, we)
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process(clk, we)
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begin
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begin
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if(rising_edge(clk)) then
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if(rising_edge(clk)) then
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if(we = '1') then
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if(we = '1') then
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ram(conv_integer(waddr)/R)(conv_integer(waddr) mod R) <= din;
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ram(conv_integer(waddr)/R)(conv_integer(waddr) mod R) <= din;
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end if;
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end if;
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q_local <= ram(conv_integer(raddr));
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q_local <= ram(conv_integer(raddr));
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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end behavorial;
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end behavorial;
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