----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- tdpram_asym ----
|
---- tdpram_asym ----
|
---- ----
|
---- ----
|
---- This file is part of the ----
|
---- This file is part of the ----
|
---- Modular Simultaneous Exponentiation Core project ----
|
---- Modular Simultaneous Exponentiation Core project ----
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
---- ----
|
---- ----
|
---- Description ----
|
---- Description ----
|
---- behavorial description of an asymmetric true dual port ----
|
---- behavorial description of an asymmetric true dual port ----
|
---- ram with one (widthA)-bit read/write port and one 32-bit ----
|
---- ram with one (widthA)-bit read/write port and one 32-bit ----
|
---- read/write port. Made using the templates of xilinx and ----
|
---- read/write port. Made using the templates of xilinx and ----
|
---- altera for asymmetric ram. ----
|
---- altera for asymmetric ram. ----
|
---- ----
|
---- ----
|
---- Dependencies: none ----
|
---- Dependencies: none ----
|
---- ----
|
---- ----
|
---- Authors: ----
|
---- Authors: ----
|
---- - Geoffrey Ottoy, DraMCo research group ----
|
---- - Geoffrey Ottoy, DraMCo research group ----
|
---- - Jonas De Craene, JonasDC@opencores.org ----
|
---- - Jonas De Craene, JonasDC@opencores.org ----
|
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
|
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- ----
|
---- ----
|
---- This source file is free software; you can redistribute it ----
|
---- This source file is free software; you can redistribute it ----
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
|
---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
|
---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- ----
|
---- ----
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
library mod_sim_exp;
|
library mod_sim_exp;
|
use mod_sim_exp.std_functions.all;
|
use mod_sim_exp.std_functions.all;
|
|
|
-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition
|
-- altera infers ramblocks from a depth of 9 (or 2 with any ram size recognition
|
-- option on or contstraint below on) and widthA 1,2,4,8,16
|
-- option on or contstraint below on) and widthA 1,2,4,8,16
|
-- xilinx infers ramblocks from a depth of 2 and widthA 1,2,4,8,16,32
|
-- xilinx infers ramblocks from a depth of 2 and widthA 1,2,4,8,16,32
|
entity tdpram_asym is
|
entity tdpram_asym is
|
generic (
|
generic (
|
depthB : integer := 4; -- nr of 32-bit words
|
depthB : integer := 4; -- nr of 32-bit words
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
widthA : integer := 2; -- port A width, must be smaller than or equal to 32
|
device : string := "xilinx"
|
device : string := "xilinx"
|
);
|
);
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
-- port A (widthA)-bit
|
-- port A (widthA)-bit
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
addrA : in std_logic_vector(log2((depthB*32)/widthA)-1 downto 0);
|
weA : in std_logic;
|
weA : in std_logic;
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
dinA : in std_logic_vector(widthA-1 downto 0);
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
doutA : out std_logic_vector(widthA-1 downto 0);
|
-- port B 32-bit
|
-- port B 32-bit
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
addrB : in std_logic_vector(log2(depthB)-1 downto 0);
|
weB : in std_logic;
|
weB : in std_logic;
|
dinB : in std_logic_vector(31 downto 0);
|
dinB : in std_logic_vector(31 downto 0);
|
doutB : out std_logic_vector(31 downto 0)
|
doutB : out std_logic_vector(31 downto 0)
|
);
|
);
|
end tdpram_asym;
|
end tdpram_asym;
|
|
|
architecture behavorial of tdpram_asym is
|
architecture behavorial of tdpram_asym is
|
-- constants
|
-- constants
|
constant R : natural := 32/widthA; -- ratio
|
constant R : natural := 32/widthA; -- ratio
|
begin
|
begin
|
|
|
xilinx_device : if device="xilinx" generate
|
xilinx_device : if device="xilinx" generate
|
-- An asymmetric RAM is modelled in a similar way as a symmetric RAM, with an
|
-- An asymmetric RAM is modelled in a similar way as a symmetric RAM, with an
|
-- array of array object. Its aspect ratio corresponds to the port with the
|
-- array of array object. Its aspect ratio corresponds to the port with the
|
-- lower data width (larger depth)
|
-- lower data width (larger depth)
|
type ramType is array (0 to ((depthB*32)/widthA)-1) of std_logic_vector(widthA-1 downto 0);
|
type ramType is array (0 to ((depthB*32)/widthA)-1) of std_logic_vector(widthA-1 downto 0);
|
|
|
-- You need to declare ram as a shared variable when :
|
-- You need to declare ram as a shared variable when :
|
-- - the RAM has two write ports,
|
-- - the RAM has two write ports,
|
-- - the RAM has only one write port whose data width is maxWIDTH
|
-- - the RAM has only one write port whose data width is maxWIDTH
|
-- In all other cases, ram can be a signal.
|
-- In all other cases, ram can be a signal.
|
shared variable ram : ramType := (others => (others => '0'));
|
shared variable ram : ramType := (others => (others => '0'));
|
signal clkA : std_logic;
|
signal clkA : std_logic;
|
signal clkB : std_logic;
|
signal clkB : std_logic;
|
|
|
begin
|
begin
|
clkA <= clk;
|
clkA <= clk;
|
process (clkA)
|
process (clkA)
|
begin
|
begin
|
if rising_edge(clkA) then
|
if rising_edge(clkA) then
|
if weA = '1' then
|
if weA = '1' then
|
ram(conv_integer(addrA)) := dinA;
|
ram(conv_integer(addrA)) := dinA;
|
end if;
|
end if;
|
doutA <= ram(conv_integer(addrA));
|
doutA <= ram(conv_integer(addrA));
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
clkB <= clk;
|
clkB <= clk;
|
process (clkB)
|
process (clkB)
|
begin
|
begin
|
if rising_edge(clkB) then
|
if rising_edge(clkB) then
|
for i in 0 to R-1 loop
|
for i in 0 to R-1 loop
|
if weB = '1' then
|
if weB = '1' then
|
ram(conv_integer(addrB & conv_std_logic_vector(i,log2(R))))
|
ram(conv_integer(addrB & conv_std_logic_vector(i,log2(R))))
|
:= dinB((i+1)*widthA-1 downto i*widthA);
|
:= dinB((i+1)*widthA-1 downto i*widthA);
|
end if;
|
end if;
|
doutB((i+1)*widthA-1 downto i*widthA)
|
doutB((i+1)*widthA-1 downto i*widthA)
|
<= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(R))));
|
<= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(R))));
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
altera_device : if device="altera" generate
|
altera_device : if device="altera" generate
|
-- Use a multidimensional array to model mixed-width
|
-- Use a multidimensional array to model mixed-width
|
type word_t is array(R-1 downto 0) of std_logic_vector(widthA-1 downto 0);
|
type word_t is array(R-1 downto 0) of std_logic_vector(widthA-1 downto 0);
|
type ram_t is array (0 to depthB-1) of word_t;
|
type ram_t is array (0 to depthB-1) of word_t;
|
|
|
-- altera constraints:
|
-- altera constraints:
|
-- for smal depths:
|
-- for smal depths:
|
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
|
-- if the synthesis option "allow any size of RAM to be inferred" is on, these lines
|
-- may be left commented.
|
-- may be left commented.
|
-- uncomment this attribute if that option is off and you know wich primitives should be used.
|
-- uncomment this attribute if that option is off and you know wich primitives should be used.
|
--attribute ramstyle : string;
|
--attribute ramstyle : string;
|
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
|
--attribute ramstyle of RAM : signal is "M9K, no_rw_check";
|
|
|
-- delcare the RAM
|
-- delcare the RAM
|
signal ram : ram_t;
|
signal ram : ram_t;
|
signal wB_local : word_t;
|
signal wB_local : word_t;
|
signal qB_local : word_t;
|
signal qB_local : word_t;
|
|
|
begin -- rtl
|
begin -- rtl
|
-- Re-organize the write data to match the RAM word type
|
-- Re-organize the write data to match the RAM word type
|
unpack: for i in 0 to R-1 generate
|
unpack: for i in 0 to R-1 generate
|
wB_local(i) <= dinB(widthA*(i+1)-1 downto widthA*i);
|
wB_local(i) <= dinB(widthA*(i+1)-1 downto widthA*i);
|
doutB(widthA*(i+1)-1 downto widthA*i) <= qB_local(i);
|
doutB(widthA*(i+1)-1 downto widthA*i) <= qB_local(i);
|
end generate unpack;
|
end generate unpack;
|
|
|
--port B
|
--port B
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if(rising_edge(clk)) then
|
if(rising_edge(clk)) then
|
if(weB = '1') then
|
if(weB = '1') then
|
ram(conv_integer(addrB)) <= wB_local;
|
ram(conv_integer(addrB)) <= wB_local;
|
end if;
|
end if;
|
qB_local <= ram(conv_integer(addrB));
|
qB_local <= ram(conv_integer(addrB));
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- port A
|
-- port A
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if(rising_edge(clk)) then
|
if(rising_edge(clk)) then
|
doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R);
|
doutA <= ram(conv_integer(addrA) / R )(conv_integer(addrA) mod R);
|
if(weA ='1') then
|
if(weA ='1') then
|
ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA;
|
ram(conv_integer(addrA) / R)(conv_integer(addrA) mod R) <= dinA;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate;
|
end generate;
|
|
|
end behavorial;
|
end behavorial;
|
|
|
|
|