------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: adder_block.vhd / entity adder_block
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-- Module Name: adder_block.vhd / entity adder_block
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--
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--
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-- Last Modified: 25/11/2011
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-- Last Modified: 25/11/2011
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--
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--
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-- Description: adder block for use in the montgommery multiplier pre- and post-
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-- Description: adder block for use in the montgommery multiplier pre- and post-
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-- computation adders
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-- computation adders
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--
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--
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--
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--
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-- Dependencies: cell_1b_adder,
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-- Dependencies: cell_1b_adder,
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-- d_flip_flop
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-- d_flip_flop
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity adder_block is
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entity adder_block is
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generic ( width : integer := 32
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generic ( width : integer := 32
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);
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);
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Port ( core_clk : in STD_LOGIC;
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Port ( core_clk : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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b : in STD_LOGIC_VECTOR((width-1) downto 0);
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b : in STD_LOGIC_VECTOR((width-1) downto 0);
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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s : out STD_LOGIC_VECTOR((width-1) downto 0)
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s : out STD_LOGIC_VECTOR((width-1) downto 0)
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);
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);
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end adder_block;
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end adder_block;
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architecture Structural of adder_block is
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architecture Structural of adder_block is
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component cell_1b_adder
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component cell_1b_adder
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Port ( a : in STD_LOGIC;
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Port ( a : in STD_LOGIC;
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mux_result : in STD_LOGIC;
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mux_result : in STD_LOGIC;
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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r : out STD_LOGIC);
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r : out STD_LOGIC);
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end component;
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end component;
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component d_flip_flop
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component d_flip_flop
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end component;
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end component;
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signal carry : std_logic_vector(width downto 0);
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signal carry : std_logic_vector(width downto 0);
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begin
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begin
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carry(0) <= cin;
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carry(0) <= cin;
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adder_chain: for i in 0 to (width-1) generate
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adder_chain: for i in 0 to (width-1) generate
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adders: cell_1b_adder
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adders: cell_1b_adder
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port map(a => a(i),
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port map(a => a(i),
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mux_result => b(i),
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mux_result => b(i),
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cin => carry(i),
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cin => carry(i),
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cout => carry(i+1),
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cout => carry(i+1),
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r => s(i)
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r => s(i)
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);
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);
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end generate;
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end generate;
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delay_1_cycle: d_flip_flop
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delay_1_cycle: d_flip_flop
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port map(core_clk => core_clk,
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port map(core_clk => core_clk,
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reset => '0',
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reset => '0',
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din => carry(width),
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din => carry(width),
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dout => cout
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dout => cout
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);
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);
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