------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: cell_1b.vhd / entity cell_1b
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-- Module Name: cell_1b.vhd / entity cell_1b
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--
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--
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-- Last Modified: 14/11/2011
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-- Last Modified: 14/11/2011
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--
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--
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-- Description: cell for use in the montgommery multiplier systolic array
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-- Description: cell for use in the montgommery multiplier systolic array
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--
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--
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--
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--
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-- Dependencies: cell_1b_adder
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-- Dependencies: cell_1b_adder
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-- cell_1b_mux
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-- cell_1b_mux
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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|
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity cell_1b is
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entity cell_1b is
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Port ( my : in STD_LOGIC;
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Port ( my : in STD_LOGIC;
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y : in STD_LOGIC;
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y : in STD_LOGIC;
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m : in STD_LOGIC;
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m : in STD_LOGIC;
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x : in STD_LOGIC;
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x : in STD_LOGIC;
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q : in STD_LOGIC;
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q : in STD_LOGIC;
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a : in STD_LOGIC;
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a : in STD_LOGIC;
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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r : out STD_LOGIC);
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r : out STD_LOGIC);
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end cell_1b;
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end cell_1b;
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architecture Structural of cell_1b is
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architecture Structural of cell_1b is
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component cell_1b_mux
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component cell_1b_mux
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Port ( my : in STD_LOGIC;
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Port ( my : in STD_LOGIC;
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y : in STD_LOGIC;
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y : in STD_LOGIC;
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m : in STD_LOGIC;
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m : in STD_LOGIC;
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x : in STD_LOGIC;
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x : in STD_LOGIC;
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q : in STD_LOGIC;
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q : in STD_LOGIC;
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result : out STD_LOGIC);
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result : out STD_LOGIC);
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end component;
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end component;
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component cell_1b_adder
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component cell_1b_adder
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Port ( a : in STD_LOGIC;
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Port ( a : in STD_LOGIC;
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mux_result : in STD_LOGIC;
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mux_result : in STD_LOGIC;
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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r : out STD_LOGIC);
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r : out STD_LOGIC);
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end component;
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end component;
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signal mux2adder : std_logic;
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signal mux2adder : std_logic;
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begin
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begin
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cell_mux: cell_1b_mux
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cell_mux: cell_1b_mux
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port map( my => my,
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port map( my => my,
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y => y,
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y => y,
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m => m,
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m => m,
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x => x,
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x => x,
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q => q,
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q => q,
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result => mux2adder
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result => mux2adder
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);
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);
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cell_adder: cell_1b_adder
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cell_adder: cell_1b_adder
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port map(a => a,
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port map(a => a,
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mux_result => mux2adder,
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mux_result => mux2adder,
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cin => cin,
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cin => cin,
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cout => cout,
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cout => cout,
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r => r
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r => r
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);
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);
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