------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: counter_sync.vhd / entity counter_sync
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-- Module Name: counter_sync.vhd / entity counter_sync
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--
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--
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-- Last Modified: 23/01/2012
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-- Last Modified: 23/01/2012
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--
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--
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-- Description: counter with synchronous count enable. It generates an
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-- Description: counter with synchronous count enable. It generates an
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-- overflow when max_value is reached
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-- overflow when max_value is reached
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--
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--
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--
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--
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-- Dependencies: none
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-- Dependencies: none
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 2.00 - moved max_value from generic to port so it is changeable in runtime
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-- Revision 2.00 - moved max_value from generic to port so it is changeable in runtime
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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|
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity counter_sync is
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entity counter_sync is
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generic(max_value : integer := 1024
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generic(max_value : integer := 1024
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);
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);
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port(reset_value : in integer;
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port(reset_value : in integer;
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core_clk : in STD_LOGIC;
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core_clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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ce : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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overflow : out STD_LOGIC
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overflow : out STD_LOGIC
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);
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);
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end counter_sync;
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end counter_sync;
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architecture Behavioral of counter_sync is
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architecture Behavioral of counter_sync is
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|
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signal overflow_i : std_logic := '0';
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signal overflow_i : std_logic := '0';
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begin
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begin
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|
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overflow <= overflow_i;
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overflow <= overflow_i;
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COUNT_PROC: process(core_clk, ce, reset)
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COUNT_PROC: process(core_clk, ce, reset)
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variable steps_counter : integer range 0 to max_value-1 := 0;
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variable steps_counter : integer range 0 to max_value-1 := 0;
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begin
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begin
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if reset = '1' then -- reset counter
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if reset = '1' then -- reset counter
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steps_counter := 0;
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steps_counter := 0;
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overflow_i <= '0';
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overflow_i <= '0';
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elsif rising_edge(core_clk) then
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elsif rising_edge(core_clk) then
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if ce = '1' then -- count
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if ce = '1' then -- count
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if steps_counter = (reset_value-1) then -- generate overflow and reset counter
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if steps_counter = (reset_value-1) then -- generate overflow and reset counter
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steps_counter := 0;
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steps_counter := 0;
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overflow_i <= '1';
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overflow_i <= '1';
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else -- just count
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else -- just count
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steps_counter := steps_counter + 1;
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steps_counter := steps_counter + 1;
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overflow_i <= '0';
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overflow_i <= '0';
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end if;
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end if;
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else
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else
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overflow_i <= '0';
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overflow_i <= '0';
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steps_counter := steps_counter;
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steps_counter := steps_counter;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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