------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: d_flip_flop.vhd / entity d_flip_flop
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-- Module Name: d_flip_flop.vhd / entity d_flip_flop
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--
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--
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-- Last Modified: 24/11/2011
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-- Last Modified: 24/11/2011
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--
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--
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-- Description: 1 bit D flip-flop
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-- Description: 1 bit D flip-flop
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--
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--
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--
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--
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-- Dependencies: LDCE
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-- Dependencies: LDCE
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity d_flip_flop is
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entity d_flip_flop is
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end d_flip_flop;
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end d_flip_flop;
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architecture Structural of d_flip_flop is
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architecture Structural of d_flip_flop is
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signal dout_i : std_logic;
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signal dout_i : std_logic;
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begin
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begin
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dout <= dout_i;
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dout <= dout_i;
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FDCE_inst : FDCE
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FDCE_inst : FDCE
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generic map (
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generic map (
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INIT => '0') -- Initial value of latch ('0' or '1')
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INIT => '0') -- Initial value of latch ('0' or '1')
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port map (
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port map (
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Q => dout_i, -- Data output
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Q => dout_i, -- Data output
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CLR => reset, -- Asynchronous clear/reset input
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CLR => reset, -- Asynchronous clear/reset input
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D => din, -- Data input
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D => din, -- Data input
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C => core_clk, -- Gate input
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C => core_clk, -- Gate input
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CE => '1' -- Gate enable input
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CE => '1' -- Gate enable input
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);
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);
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