------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: first_stage.vhd / entity first_stage
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-- Module Name: first_stage.vhd / entity first_stage
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--
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--
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-- Last Modified: 24/11/2011
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-- Last Modified: 24/11/2011
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--
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--
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-- Description: first stage for use in the montgommery multiplier systolic
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-- Description: first stage for use in the montgommery multiplier systolic
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-- array pipeline
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-- array pipeline
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--
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--
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--
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--
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-- Dependencies: standard_cell_block
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-- Dependencies: standard_cell_block
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-- cell_mux_1b
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-- cell_mux_1b
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-- register_n,
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-- register_n,
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-- register_1b,
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-- register_1b,
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-- d_flip_flop
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-- d_flip_flop
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 4.00 - Removed input registers and used start signal as load_out_regs
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-- Revision 4.00 - Removed input registers and used start signal as load_out_regs
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-- Revision 3.00 - Removed "a" input and replaced with "a_msb" (which is the only one
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-- Revision 3.00 - Removed "a" input and replaced with "a_msb" (which is the only one
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-- that matters.
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-- that matters.
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-- Revision 2.02 - removed "ready" output signal
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-- Revision 2.02 - removed "ready" output signal
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-- Revision 2.01 - replaced the behavioral description of the registers with a
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-- Revision 2.01 - replaced the behavioral description of the registers with a
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-- component instantiation
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-- component instantiation
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-- Revision 2.00 - added register to store input value xin (because this
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-- Revision 2.00 - added register to store input value xin (because this
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-- can change during operation)
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-- can change during operation)
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-- Revision 1.03 - added done pulse
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-- Revision 1.03 - added done pulse
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-- Revision 1.02 - appended "_i" to name of all internal signals
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-- Revision 1.02 - appended "_i" to name of all internal signals
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-- Revision 1.01 - ready is '1' after reset
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-- Revision 1.01 - ready is '1' after reset
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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|
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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|
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entity first_stage is
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entity first_stage is
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generic(width : integer := 16 -- must be the same as width of the standard stage
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generic(width : integer := 16 -- must be the same as width of the standard stage
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);
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);
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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my : in STD_LOGIC_VECTOR((width) downto 0);
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my : in STD_LOGIC_VECTOR((width) downto 0);
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y : in STD_LOGIC_VECTOR((width) downto 0);
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y : in STD_LOGIC_VECTOR((width) downto 0);
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m : in STD_LOGIC_VECTOR((width) downto 0);
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m : in STD_LOGIC_VECTOR((width) downto 0);
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xin : in STD_LOGIC;
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xin : in STD_LOGIC;
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xout : out STD_LOGIC;
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xout : out STD_LOGIC;
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qout : out STD_LOGIC;
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qout : out STD_LOGIC;
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a_msb : in STD_LOGIC;
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a_msb : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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-- ready : out STD_LOGIC;
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-- ready : out STD_LOGIC;
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done : out STD_LOGIC;
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done : out STD_LOGIC;
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r : out STD_LOGIC_VECTOR((width-1) downto 0)
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r : out STD_LOGIC_VECTOR((width-1) downto 0)
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);
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);
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end first_stage;
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end first_stage;
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|
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architecture Structural of first_stage is
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architecture Structural of first_stage is
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|
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component d_flip_flop
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component d_flip_flop
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end component;
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end component;
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|
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component register_1b
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component register_1b
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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ce : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end component;
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end component;
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|
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component register_n
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component register_n
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generic( n : integer := 4
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generic( n : integer := 4
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);
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);
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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ce : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC_VECTOR((n-1) downto 0);
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din : in STD_LOGIC_VECTOR((n-1) downto 0);
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dout : out STD_LOGIC_VECTOR((n-1) downto 0)
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dout : out STD_LOGIC_VECTOR((n-1) downto 0)
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);
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);
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end component;
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end component;
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|
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component standard_cell_block
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component standard_cell_block
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generic ( width : integer := 32
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generic ( width : integer := 32
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);
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);
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Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
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Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
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y : in STD_LOGIC_VECTOR((width-1) downto 0);
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y : in STD_LOGIC_VECTOR((width-1) downto 0);
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m : in STD_LOGIC_VECTOR((width-1) downto 0);
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m : in STD_LOGIC_VECTOR((width-1) downto 0);
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x : in STD_LOGIC;
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x : in STD_LOGIC;
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q : in STD_LOGIC;
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q : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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r : out STD_LOGIC_VECTOR((width-1) downto 0));
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r : out STD_LOGIC_VECTOR((width-1) downto 0));
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end component;
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end component;
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|
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component cell_1b_mux
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component cell_1b_mux
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port ( my : in STD_LOGIC;
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port ( my : in STD_LOGIC;
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y : in STD_LOGIC;
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y : in STD_LOGIC;
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m : in STD_LOGIC;
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m : in STD_LOGIC;
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x : in STD_LOGIC;
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x : in STD_LOGIC;
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q : in STD_LOGIC;
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q : in STD_LOGIC;
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result : out STD_LOGIC);
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result : out STD_LOGIC);
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end component;
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end component;
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|
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-- input
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-- input
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signal xin_i : std_logic;
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signal xin_i : std_logic;
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signal a_msb_i : std_logic;
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signal a_msb_i : std_logic;
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-- signal xin_reg_i : std_logic;
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-- signal xin_reg_i : std_logic;
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-- signal a_msb_reg_i : std_logic;
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-- signal a_msb_reg_i : std_logic;
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|
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-- output
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-- output
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signal cout_i : std_logic;
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signal cout_i : std_logic;
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signal r_i : std_logic_vector((width-1) downto 0);
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signal r_i : std_logic_vector((width-1) downto 0);
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signal cout_reg_i : std_logic;
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signal cout_reg_i : std_logic;
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signal xout_reg_i : std_logic;
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signal xout_reg_i : std_logic;
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signal qout_reg_i : std_logic;
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signal qout_reg_i : std_logic;
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signal r_reg_i : std_logic_vector((width-1) downto 0);
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signal r_reg_i : std_logic_vector((width-1) downto 0);
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|
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-- interconnection
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-- interconnection
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signal q_i : std_logic;
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signal q_i : std_logic;
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signal c_i : std_logic;
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signal c_i : std_logic;
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signal first_res_i : std_logic;
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signal first_res_i : std_logic;
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signal a_i : std_logic_vector((width) downto 0);
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signal a_i : std_logic_vector((width) downto 0);
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|
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-- control signals
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-- control signals
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signal done_i : std_logic := '1';
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signal done_i : std_logic := '1';
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--signal ready_del_i : std_logic := '1';
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--signal ready_del_i : std_logic := '1';
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-- signal load_out_regs_i : std_logic;
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-- signal load_out_regs_i : std_logic;
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begin
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begin
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|
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-- map inputs to internal signals
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-- map inputs to internal signals
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xin_i <= xin;
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xin_i <= xin;
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a_msb_i <= a_msb;
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a_msb_i <= a_msb;
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|
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-- map internal signals to outputs
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-- map internal signals to outputs
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done <= done_i;
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done <= done_i;
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r <= r_reg_i;
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r <= r_reg_i;
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cout <= cout_reg_i;
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cout <= cout_reg_i;
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qout <= qout_reg_i;
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qout <= qout_reg_i;
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xout <= xout_reg_i;
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xout <= xout_reg_i;
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-- two posibilities:
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-- two posibilities:
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--done <= ready_i and (not ready_del_i); -- slow
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--done <= ready_i and (not ready_del_i); -- slow
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--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
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--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
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|
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-- a_i <= a_msb_reg_i & r_reg_i;
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-- a_i <= a_msb_reg_i & r_reg_i;
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a_i <= a_msb_i & r_reg_i;
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a_i <= a_msb_i & r_reg_i;
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|
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-- -- input registers
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-- -- input registers
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-- A_REG: register_1b
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-- A_REG: register_1b
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- ce => start,
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-- ce => start,
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-- reset => reset,
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-- reset => reset,
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-- din => a_msb_i,
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-- din => a_msb_i,
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-- dout => a_msb_reg_i
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-- dout => a_msb_reg_i
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-- );
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-- );
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--
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--
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-- XIN_REG: register_1b
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-- XIN_REG: register_1b
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- ce => start,
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-- ce => start,
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-- reset => reset,
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-- reset => reset,
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-- din => xin_i,
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-- din => xin_i,
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-- dout => xin_reg_i
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-- dout => xin_reg_i
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-- );
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-- );
|
|
|
-- compute first q_i and carry
|
-- compute first q_i and carry
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-- q_i <= a_i(0) xor (y(0) and xin_reg_i);
|
-- q_i <= a_i(0) xor (y(0) and xin_reg_i);
|
q_i <= a_i(0) xor (y(0) and xin_i);
|
q_i <= a_i(0) xor (y(0) and xin_i);
|
c_i <= a_i(0) and first_res_i;
|
c_i <= a_i(0) and first_res_i;
|
|
|
first_cell: cell_1b_mux
|
first_cell: cell_1b_mux
|
port map( my => my(0),
|
port map( my => my(0),
|
y => y(0),
|
y => y(0),
|
m => m(0),
|
m => m(0),
|
-- x => xin_reg_i,
|
-- x => xin_reg_i,
|
x => xin_i,
|
x => xin_i,
|
q => q_i,
|
q => q_i,
|
result => first_res_i
|
result => first_res_i
|
);
|
);
|
|
|
cell_block: standard_cell_block
|
cell_block: standard_cell_block
|
generic map( width => width
|
generic map( width => width
|
)
|
)
|
port map( my => my(width downto 1),
|
port map( my => my(width downto 1),
|
y => y(width downto 1),
|
y => y(width downto 1),
|
m => m(width downto 1),
|
m => m(width downto 1),
|
-- x => xin_reg_i,
|
-- x => xin_reg_i,
|
x => xin_i,
|
x => xin_i,
|
q => q_i,
|
q => q_i,
|
a => a_i(width downto 1),
|
a => a_i(width downto 1),
|
cin => c_i,
|
cin => c_i,
|
cout => cout_i,
|
cout => cout_i,
|
r => r_i((width-1) downto 0)
|
r => r_i((width-1) downto 0)
|
);
|
);
|
|
|
-- delay_1_cycle: d_flip_flop
|
-- delay_1_cycle: d_flip_flop
|
-- port map(core_clk => core_clk,
|
-- port map(core_clk => core_clk,
|
-- reset => reset,
|
-- reset => reset,
|
-- din => start,
|
-- din => start,
|
-- dout => load_out_regs_i
|
-- dout => load_out_regs_i
|
-- );
|
-- );
|
|
|
done_signal: d_flip_flop
|
done_signal: d_flip_flop
|
port map(core_clk => core_clk,
|
port map(core_clk => core_clk,
|
reset => reset,
|
reset => reset,
|
-- din => load_out_regs_i,
|
-- din => load_out_regs_i,
|
din => start,
|
din => start,
|
dout => done_i
|
dout => done_i
|
);
|
);
|
|
|
-- output registers
|
-- output registers
|
RESULT_REG: register_n
|
RESULT_REG: register_n
|
generic map( n => width
|
generic map( n => width
|
)
|
)
|
port map(core_clk => core_clk,
|
port map(core_clk => core_clk,
|
-- ce => load_out_regs_i,
|
-- ce => load_out_regs_i,
|
ce => start,
|
ce => start,
|
reset => reset,
|
reset => reset,
|
din => r_i,
|
din => r_i,
|
dout => r_reg_i
|
dout => r_reg_i
|
);
|
);
|
|
|
XOUT_REG: register_1b
|
XOUT_REG: register_1b
|
port map(core_clk => core_clk,
|
port map(core_clk => core_clk,
|
-- ce => load_out_regs_i,
|
-- ce => load_out_regs_i,
|
ce => start,
|
ce => start,
|
reset => reset,
|
reset => reset,
|
-- din => xin_reg_i,
|
-- din => xin_reg_i,
|
din => xin_i,
|
din => xin_i,
|
dout => xout_reg_i
|
dout => xout_reg_i
|
);
|
);
|
|
|
QOUT_REG: register_1b
|
QOUT_REG: register_1b
|
port map(core_clk => core_clk,
|
port map(core_clk => core_clk,
|
-- ce => load_out_regs_i,
|
-- ce => load_out_regs_i,
|
ce => start,
|
ce => start,
|
reset => reset,
|
reset => reset,
|
din => q_i,
|
din => q_i,
|
dout => qout_reg_i
|
dout => qout_reg_i
|
);
|
);
|
|
|
COUT_REG: register_1b
|
COUT_REG: register_1b
|
port map(core_clk => core_clk,
|
port map(core_clk => core_clk,
|
-- ce => load_out_regs_i,
|
-- ce => load_out_regs_i,
|
ce => start,
|
ce => start,
|
reset => reset,
|
reset => reset,
|
din => cout_i,
|
din => cout_i,
|
dout => cout_reg_i
|
dout => cout_reg_i
|
);
|
);
|
|
|
|
|
