------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------
|
--
|
--
|
-- Geoffrey Ottoy - DraMCo research group
|
-- Geoffrey Ottoy - DraMCo research group
|
--
|
--
|
-- Module Name: last_stage.vhd / entity last_stage
|
-- Module Name: last_stage.vhd / entity last_stage
|
--
|
--
|
-- Last Modified: 24/11/2011
|
-- Last Modified: 24/11/2011
|
--
|
--
|
-- Description: last stage for use in the montgommery multiplier systolic
|
-- Description: last stage for use in the montgommery multiplier systolic
|
-- array pipeline
|
-- array pipeline
|
--
|
--
|
--
|
--
|
-- Dependencies: standard_cell_block
|
-- Dependencies: standard_cell_block
|
-- cell_1b
|
-- cell_1b
|
--
|
--
|
-- Revision:
|
-- Revision:
|
-- Revision 5.00 - Removed input registers and used start signal as load_out_regs
|
-- Revision 5.00 - Removed input registers and used start signal as load_out_regs
|
-- Revision 4.01 - Remove "done" input
|
-- Revision 4.01 - Remove "done" input
|
-- Revision 4.00 - Removed "a" input with internal feedback
|
-- Revision 4.00 - Removed "a" input with internal feedback
|
-- Revision 3.03 - fixed switched last two bits
|
-- Revision 3.03 - fixed switched last two bits
|
-- Revision 3.02 - removed "ready" output signal
|
-- Revision 3.02 - removed "ready" output signal
|
-- Revision 3.01 - replaced the behavioral description of the registers with a
|
-- Revision 3.01 - replaced the behavioral description of the registers with a
|
-- component instantiation
|
-- component instantiation
|
-- Revision 3.00 - added registers to store input values xin, cin, qin (because they
|
-- Revision 3.00 - added registers to store input values xin, cin, qin (because they
|
-- can change during operation)
|
-- can change during operation)
|
-- Revision 2.00 - changed indices in signals my, y and m
|
-- Revision 2.00 - changed indices in signals my, y and m
|
-- Revision 1.03 - added done pulse
|
-- Revision 1.03 - added done pulse
|
-- Revision 1.02 - appended "_i" to name of all internal signals
|
-- Revision 1.02 - appended "_i" to name of all internal signals
|
-- Revision 1.01 - ready is '1' after reset
|
-- Revision 1.01 - ready is '1' after reset
|
-- Revision 1.00 - Architecture
|
-- Revision 1.00 - Architecture
|
-- Revision 0.01 - File Created
|
-- Revision 0.01 - File Created
|
--
|
--
|
--
|
--
|
------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------
|
--
|
--
|
-- NOTICE:
|
-- NOTICE:
|
--
|
--
|
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
|
-- Copyright DraMCo research group. 2011. This code may be contain portions patented
|
-- by other third parties!
|
-- by other third parties!
|
--
|
--
|
------------------------------------------------------------------------------------
|
------------------------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
---- Uncomment the following library declaration if instantiating
|
---- Uncomment the following library declaration if instantiating
|
---- any Xilinx primitives in this code.
|
---- any Xilinx primitives in this code.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity last_stage is
|
entity last_stage is
|
generic(width : integer := 16 -- must be the same as width of the standard stage
|
generic(width : integer := 16 -- must be the same as width of the standard stage
|
);
|
);
|
port(core_clk : in STD_LOGIC;
|
port(core_clk : in STD_LOGIC;
|
my : in STD_LOGIC_VECTOR((width-1) downto 0);
|
my : in STD_LOGIC_VECTOR((width-1) downto 0);
|
y : in STD_LOGIC_VECTOR((width-2) downto 0);
|
y : in STD_LOGIC_VECTOR((width-2) downto 0);
|
m : in STD_LOGIC_VECTOR((width-2) downto 0);
|
m : in STD_LOGIC_VECTOR((width-2) downto 0);
|
xin : in STD_LOGIC;
|
xin : in STD_LOGIC;
|
qin : in STD_LOGIC;
|
qin : in STD_LOGIC;
|
cin : in STD_LOGIC;
|
cin : in STD_LOGIC;
|
start : in STD_LOGIC;
|
start : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
-- ready : out STD_LOGIC;
|
-- ready : out STD_LOGIC;
|
-- done : out STD_LOGIC;
|
-- done : out STD_LOGIC;
|
r : out STD_LOGIC_VECTOR((width+1) downto 0)
|
r : out STD_LOGIC_VECTOR((width+1) downto 0)
|
);
|
);
|
end last_stage;
|
end last_stage;
|
|
|
architecture Structural of last_stage is
|
architecture Structural of last_stage is
|
|
|
component d_flip_flop
|
component d_flip_flop
|
port(core_clk : in STD_LOGIC;
|
port(core_clk : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
din : in STD_LOGIC;
|
din : in STD_LOGIC;
|
dout : out STD_LOGIC
|
dout : out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
component register_1b
|
component register_1b
|
port(core_clk : in STD_LOGIC;
|
port(core_clk : in STD_LOGIC;
|
ce : in STD_LOGIC;
|
ce : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
din : in STD_LOGIC;
|
din : in STD_LOGIC;
|
dout : out STD_LOGIC
|
dout : out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
component register_n
|
component register_n
|
generic( n : integer := 4
|
generic( n : integer := 4
|
);
|
);
|
port(core_clk : in STD_LOGIC;
|
port(core_clk : in STD_LOGIC;
|
ce : in STD_LOGIC;
|
ce : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
din : in STD_LOGIC_VECTOR((n-1) downto 0);
|
din : in STD_LOGIC_VECTOR((n-1) downto 0);
|
dout : out STD_LOGIC_VECTOR((n-1) downto 0)
|
dout : out STD_LOGIC_VECTOR((n-1) downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component standard_cell_block
|
component standard_cell_block
|
generic ( width : integer := 32
|
generic ( width : integer := 32
|
);
|
);
|
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
|
Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
|
y : in STD_LOGIC_VECTOR((width-1) downto 0);
|
y : in STD_LOGIC_VECTOR((width-1) downto 0);
|
m : in STD_LOGIC_VECTOR((width-1) downto 0);
|
m : in STD_LOGIC_VECTOR((width-1) downto 0);
|
x : in STD_LOGIC;
|
x : in STD_LOGIC;
|
q : in STD_LOGIC;
|
q : in STD_LOGIC;
|
a : in STD_LOGIC_VECTOR((width-1) downto 0);
|
a : in STD_LOGIC_VECTOR((width-1) downto 0);
|
cin : in STD_LOGIC;
|
cin : in STD_LOGIC;
|
cout : out STD_LOGIC;
|
cout : out STD_LOGIC;
|
r : out STD_LOGIC_VECTOR((width-1) downto 0));
|
r : out STD_LOGIC_VECTOR((width-1) downto 0));
|
end component;
|
end component;
|
|
|
component cell_1b
|
component cell_1b
|
port ( my : in STD_LOGIC;
|
port ( my : in STD_LOGIC;
|
y : in STD_LOGIC;
|
y : in STD_LOGIC;
|
m : in STD_LOGIC;
|
m : in STD_LOGIC;
|
x : in STD_LOGIC;
|
x : in STD_LOGIC;
|
q : in STD_LOGIC;
|
q : in STD_LOGIC;
|
a : in STD_LOGIC;
|
a : in STD_LOGIC;
|
cin : in STD_LOGIC;
|
cin : in STD_LOGIC;
|
cout : out STD_LOGIC;
|
cout : out STD_LOGIC;
|
r : out STD_LOGIC);
|
r : out STD_LOGIC);
|
end component;
|
end component;
|
|
|
-- input
|
-- input
|
signal my_i : std_logic_vector(width downto 0);
|
signal my_i : std_logic_vector(width downto 0);
|
signal m_i : std_logic_vector(width downto 0);
|
signal m_i : std_logic_vector(width downto 0);
|
signal y_i : std_logic_vector(width downto 0);
|
signal y_i : std_logic_vector(width downto 0);
|
signal cin_i : std_logic;
|
signal cin_i : std_logic;
|
signal xin_i : std_logic;
|
signal xin_i : std_logic;
|
signal qin_i : std_logic;
|
signal qin_i : std_logic;
|
signal a_i : std_logic_vector((width) downto 0);
|
signal a_i : std_logic_vector((width) downto 0);
|
-- signal cin_reg_i : std_logic;
|
-- signal cin_reg_i : std_logic;
|
-- signal xin_reg_i : std_logic;
|
-- signal xin_reg_i : std_logic;
|
-- signal qin_reg_i : std_logic;
|
-- signal qin_reg_i : std_logic;
|
-- signal a_reg_i : std_logic_vector((width) downto 0);
|
-- signal a_reg_i : std_logic_vector((width) downto 0);
|
|
|
-- output
|
-- output
|
signal r_i : std_logic_vector((width+1) downto 0);
|
signal r_i : std_logic_vector((width+1) downto 0);
|
signal r_reg_i : std_logic_vector((width+1) downto 0);
|
signal r_reg_i : std_logic_vector((width+1) downto 0);
|
|
|
-- interconnection
|
-- interconnection
|
signal cout_i : std_logic;
|
signal cout_i : std_logic;
|
|
|
-- control signals
|
-- control signals
|
-- signal load_out_regs_i : std_logic;
|
-- signal load_out_regs_i : std_logic;
|
-- signal done_i : std_logic := '1';
|
-- signal done_i : std_logic := '1';
|
--signal ready_del_i : std_logic := '1';
|
--signal ready_del_i : std_logic := '1';
|
|
|
begin
|
begin
|
-- map internal signals to outputs
|
-- map internal signals to outputs
|
-- done <= done_i;
|
-- done <= done_i;
|
r <= r_reg_i;
|
r <= r_reg_i;
|
-- two posibilities:
|
-- two posibilities:
|
--done <= ready_i and (not ready_del_i); -- slow
|
--done <= ready_i and (not ready_del_i); -- slow
|
--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
|
--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
|
|
|
-- map inputs to internal signals
|
-- map inputs to internal signals
|
my_i <= '0' & my;
|
my_i <= '0' & my;
|
m_i <= "00" & m;
|
m_i <= "00" & m;
|
y_i <= "00" & y;
|
y_i <= "00" & y;
|
xin_i <= xin;
|
xin_i <= xin;
|
qin_i <= qin;
|
qin_i <= qin;
|
cin_i <= cin;
|
cin_i <= cin;
|
|
|
a_i <= r_reg_i((width+1) downto 1);
|
a_i <= r_reg_i((width+1) downto 1);
|
|
|
cell_block: standard_cell_block
|
cell_block: standard_cell_block
|
generic map( width => width
|
generic map( width => width
|
)
|
)
|
Port map( my => my_i(width-1 downto 0),
|
Port map( my => my_i(width-1 downto 0),
|
y => y_i(width-1 downto 0),
|
y => y_i(width-1 downto 0),
|
m => m_i(width-1 downto 0),
|
m => m_i(width-1 downto 0),
|
-- x => xin_reg_i,
|
-- x => xin_reg_i,
|
-- q => qin_reg_i,
|
-- q => qin_reg_i,
|
x => xin_i,
|
x => xin_i,
|
q => qin_i,
|
q => qin_i,
|
a => a_i((width-1) downto 0),
|
a => a_i((width-1) downto 0),
|
-- cin => cin_reg_i,
|
-- cin => cin_reg_i,
|
cin => cin_i,
|
cin => cin_i,
|
cout => cout_i,
|
cout => cout_i,
|
r => r_i((width-1) downto 0)
|
r => r_i((width-1) downto 0)
|
);
|
);
|
|
|
last_cell: cell_1b
|
last_cell: cell_1b
|
port map( my => my_i(width),
|
port map( my => my_i(width),
|
y => y_i(width),
|
y => y_i(width),
|
m => m_i(width),
|
m => m_i(width),
|
-- x => xin_reg_i,
|
-- x => xin_reg_i,
|
-- q => qin_reg_i,
|
-- q => qin_reg_i,
|
x => xin_i,
|
x => xin_i,
|
q => qin_i,
|
q => qin_i,
|
a => a_i(width),
|
a => a_i(width),
|
cin => cout_i,
|
cin => cout_i,
|
cout => r_i(width+1),
|
cout => r_i(width+1),
|
r => r_i(width)
|
r => r_i(width)
|
);
|
);
|
|
|
-- XIN_REG: register_1b
|
-- XIN_REG: register_1b
|
-- port map(core_clk => core_clk,
|
-- port map(core_clk => core_clk,
|
-- ce => start,
|
-- ce => start,
|
-- reset => reset,
|
-- reset => reset,
|
-- din => xin_i,
|
-- din => xin_i,
|
-- dout => xin_reg_i
|
-- dout => xin_reg_i
|
-- );
|
-- );
|
|
|
-- QIN_REG: register_1b
|
-- QIN_REG: register_1b
|
-- port map(core_clk => core_clk,
|
-- port map(core_clk => core_clk,
|
-- ce => start,
|
-- ce => start,
|
-- reset => reset,
|
-- reset => reset,
|
-- din => qin_i,
|
-- din => qin_i,
|
-- dout => qin_reg_i
|
-- dout => qin_reg_i
|
-- );
|
-- );
|
|
|
-- CIN_REG: register_1b
|
-- CIN_REG: register_1b
|
-- port map(core_clk => core_clk,
|
-- port map(core_clk => core_clk,
|
-- ce => start,
|
-- ce => start,
|
-- reset => reset,
|
-- reset => reset,
|
-- din => cin_i,
|
-- din => cin_i,
|
-- dout => cin_reg_i
|
-- dout => cin_reg_i
|
-- );
|
-- );
|
|
|
-- control
|
-- control
|
-- delay_1_cycle: d_flip_flop
|
-- delay_1_cycle: d_flip_flop
|
-- port map(core_clk => core_clk,
|
-- port map(core_clk => core_clk,
|
-- reset => reset,
|
-- reset => reset,
|
-- din => start,
|
-- din => start,
|
-- dout => load_out_regs_i
|
-- dout => load_out_regs_i
|
-- );
|
-- );
|
|
|
-- done_signal: d_flip_flop
|
-- done_signal: d_flip_flop
|
-- port map(core_clk => core_clk,
|
-- port map(core_clk => core_clk,
|
-- reset => reset,
|
-- reset => reset,
|
-- din => load_out_regs_i,
|
-- din => load_out_regs_i,
|
-- dout => done_i
|
-- dout => done_i
|
-- );
|
-- );
|
|
|
-- output registers
|
-- output registers
|
RESULT_REG: register_n
|
RESULT_REG: register_n
|
generic map( n => (width+2)
|
generic map( n => (width+2)
|
)
|
)
|
port map(core_clk => core_clk,
|
port map(core_clk => core_clk,
|
-- ce => load_out_regs_i,
|
-- ce => load_out_regs_i,
|
ce => start,
|
ce => start,
|
reset => reset,
|
reset => reset,
|
din => r_i,
|
din => r_i,
|
dout => r_reg_i
|
dout => r_reg_i
|
);
|
);
|
|
|
|
|
