------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: last_stage.vhd / entity last_stage
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-- Module Name: last_stage.vhd / entity last_stage
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--
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--
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-- Last Modified: 24/11/2011
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-- Last Modified: 24/11/2011
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--
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--
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-- Description: last stage for use in the montgommery multiplier systolic
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-- Description: last stage for use in the montgommery multiplier systolic
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-- array pipeline
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-- array pipeline
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--
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--
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--
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--
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-- Dependencies: standard_cell_block
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-- Dependencies: standard_cell_block
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-- cell_1b
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-- cell_1b
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 5.00 - Removed input registers and used start signal as load_out_regs
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-- Revision 5.00 - Removed input registers and used start signal as load_out_regs
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-- Revision 4.01 - Remove "done" input
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-- Revision 4.01 - Remove "done" input
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-- Revision 4.00 - Removed "a" input with internal feedback
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-- Revision 4.00 - Removed "a" input with internal feedback
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-- Revision 3.03 - fixed switched last two bits
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-- Revision 3.03 - fixed switched last two bits
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-- Revision 3.02 - removed "ready" output signal
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-- Revision 3.02 - removed "ready" output signal
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-- Revision 3.01 - replaced the behavioral description of the registers with a
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-- Revision 3.01 - replaced the behavioral description of the registers with a
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-- component instantiation
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-- component instantiation
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-- Revision 3.00 - added registers to store input values xin, cin, qin (because they
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-- Revision 3.00 - added registers to store input values xin, cin, qin (because they
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-- can change during operation)
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-- can change during operation)
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-- Revision 2.00 - changed indices in signals my, y and m
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-- Revision 2.00 - changed indices in signals my, y and m
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-- Revision 1.03 - added done pulse
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-- Revision 1.03 - added done pulse
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-- Revision 1.02 - appended "_i" to name of all internal signals
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-- Revision 1.02 - appended "_i" to name of all internal signals
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-- Revision 1.01 - ready is '1' after reset
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-- Revision 1.01 - ready is '1' after reset
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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|
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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|
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entity last_stage is
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entity last_stage is
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generic(width : integer := 16 -- must be the same as width of the standard stage
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generic(width : integer := 16 -- must be the same as width of the standard stage
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);
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);
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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my : in STD_LOGIC_VECTOR((width-1) downto 0);
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my : in STD_LOGIC_VECTOR((width-1) downto 0);
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y : in STD_LOGIC_VECTOR((width-2) downto 0);
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y : in STD_LOGIC_VECTOR((width-2) downto 0);
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m : in STD_LOGIC_VECTOR((width-2) downto 0);
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m : in STD_LOGIC_VECTOR((width-2) downto 0);
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xin : in STD_LOGIC;
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xin : in STD_LOGIC;
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qin : in STD_LOGIC;
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qin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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-- ready : out STD_LOGIC;
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-- ready : out STD_LOGIC;
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-- done : out STD_LOGIC;
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-- done : out STD_LOGIC;
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r : out STD_LOGIC_VECTOR((width+1) downto 0)
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r : out STD_LOGIC_VECTOR((width+1) downto 0)
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);
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);
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end last_stage;
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end last_stage;
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architecture Structural of last_stage is
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architecture Structural of last_stage is
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|
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component d_flip_flop
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component d_flip_flop
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end component;
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end component;
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component register_1b
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component register_1b
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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ce : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end component;
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end component;
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component register_n
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component register_n
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generic( n : integer := 4
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generic( n : integer := 4
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);
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);
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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ce : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC_VECTOR((n-1) downto 0);
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din : in STD_LOGIC_VECTOR((n-1) downto 0);
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dout : out STD_LOGIC_VECTOR((n-1) downto 0)
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dout : out STD_LOGIC_VECTOR((n-1) downto 0)
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);
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);
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end component;
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end component;
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component standard_cell_block
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component standard_cell_block
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generic ( width : integer := 32
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generic ( width : integer := 32
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);
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);
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Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
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Port ( my : in STD_LOGIC_VECTOR((width-1) downto 0);
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y : in STD_LOGIC_VECTOR((width-1) downto 0);
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y : in STD_LOGIC_VECTOR((width-1) downto 0);
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m : in STD_LOGIC_VECTOR((width-1) downto 0);
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m : in STD_LOGIC_VECTOR((width-1) downto 0);
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x : in STD_LOGIC;
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x : in STD_LOGIC;
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q : in STD_LOGIC;
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q : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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r : out STD_LOGIC_VECTOR((width-1) downto 0));
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r : out STD_LOGIC_VECTOR((width-1) downto 0));
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end component;
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end component;
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component cell_1b
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component cell_1b
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port ( my : in STD_LOGIC;
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port ( my : in STD_LOGIC;
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y : in STD_LOGIC;
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y : in STD_LOGIC;
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m : in STD_LOGIC;
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m : in STD_LOGIC;
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x : in STD_LOGIC;
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x : in STD_LOGIC;
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q : in STD_LOGIC;
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q : in STD_LOGIC;
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a : in STD_LOGIC;
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a : in STD_LOGIC;
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cin : in STD_LOGIC;
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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cout : out STD_LOGIC;
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r : out STD_LOGIC);
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r : out STD_LOGIC);
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end component;
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end component;
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-- input
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-- input
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signal my_i : std_logic_vector(width downto 0);
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signal my_i : std_logic_vector(width downto 0);
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signal m_i : std_logic_vector(width downto 0);
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signal m_i : std_logic_vector(width downto 0);
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signal y_i : std_logic_vector(width downto 0);
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signal y_i : std_logic_vector(width downto 0);
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signal cin_i : std_logic;
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signal cin_i : std_logic;
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signal xin_i : std_logic;
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signal xin_i : std_logic;
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signal qin_i : std_logic;
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signal qin_i : std_logic;
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signal a_i : std_logic_vector((width) downto 0);
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signal a_i : std_logic_vector((width) downto 0);
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-- signal cin_reg_i : std_logic;
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-- signal cin_reg_i : std_logic;
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-- signal xin_reg_i : std_logic;
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-- signal xin_reg_i : std_logic;
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-- signal qin_reg_i : std_logic;
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-- signal qin_reg_i : std_logic;
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-- signal a_reg_i : std_logic_vector((width) downto 0);
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-- signal a_reg_i : std_logic_vector((width) downto 0);
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-- output
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-- output
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signal r_i : std_logic_vector((width+1) downto 0);
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signal r_i : std_logic_vector((width+1) downto 0);
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signal r_reg_i : std_logic_vector((width+1) downto 0);
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signal r_reg_i : std_logic_vector((width+1) downto 0);
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-- interconnection
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-- interconnection
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signal cout_i : std_logic;
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signal cout_i : std_logic;
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-- control signals
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-- control signals
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-- signal load_out_regs_i : std_logic;
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-- signal load_out_regs_i : std_logic;
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-- signal done_i : std_logic := '1';
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-- signal done_i : std_logic := '1';
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--signal ready_del_i : std_logic := '1';
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--signal ready_del_i : std_logic := '1';
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begin
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begin
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-- map internal signals to outputs
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-- map internal signals to outputs
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-- done <= done_i;
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-- done <= done_i;
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r <= r_reg_i;
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r <= r_reg_i;
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-- two posibilities:
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-- two posibilities:
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--done <= ready_i and (not ready_del_i); -- slow
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--done <= ready_i and (not ready_del_i); -- slow
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--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
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--done <= not ready_i; -- faster but not sure if it will work (DONE_PROC can be omitted)
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-- map inputs to internal signals
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-- map inputs to internal signals
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my_i <= '0' & my;
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my_i <= '0' & my;
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m_i <= "00" & m;
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m_i <= "00" & m;
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y_i <= "00" & y;
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y_i <= "00" & y;
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xin_i <= xin;
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xin_i <= xin;
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qin_i <= qin;
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qin_i <= qin;
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cin_i <= cin;
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cin_i <= cin;
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a_i <= r_reg_i((width+1) downto 1);
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a_i <= r_reg_i((width+1) downto 1);
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cell_block: standard_cell_block
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cell_block: standard_cell_block
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generic map( width => width
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generic map( width => width
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)
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)
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Port map( my => my_i(width-1 downto 0),
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Port map( my => my_i(width-1 downto 0),
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y => y_i(width-1 downto 0),
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y => y_i(width-1 downto 0),
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m => m_i(width-1 downto 0),
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m => m_i(width-1 downto 0),
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-- x => xin_reg_i,
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-- x => xin_reg_i,
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-- q => qin_reg_i,
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-- q => qin_reg_i,
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x => xin_i,
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x => xin_i,
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q => qin_i,
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q => qin_i,
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a => a_i((width-1) downto 0),
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a => a_i((width-1) downto 0),
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-- cin => cin_reg_i,
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-- cin => cin_reg_i,
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cin => cin_i,
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cin => cin_i,
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cout => cout_i,
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cout => cout_i,
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r => r_i((width-1) downto 0)
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r => r_i((width-1) downto 0)
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);
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);
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last_cell: cell_1b
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last_cell: cell_1b
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port map( my => my_i(width),
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port map( my => my_i(width),
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y => y_i(width),
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y => y_i(width),
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m => m_i(width),
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m => m_i(width),
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-- x => xin_reg_i,
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-- x => xin_reg_i,
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-- q => qin_reg_i,
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-- q => qin_reg_i,
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x => xin_i,
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x => xin_i,
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q => qin_i,
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q => qin_i,
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a => a_i(width),
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a => a_i(width),
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cin => cout_i,
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cin => cout_i,
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cout => r_i(width+1),
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cout => r_i(width+1),
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r => r_i(width)
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r => r_i(width)
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);
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);
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-- XIN_REG: register_1b
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-- XIN_REG: register_1b
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- ce => start,
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-- ce => start,
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-- reset => reset,
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-- reset => reset,
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-- din => xin_i,
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-- din => xin_i,
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-- dout => xin_reg_i
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-- dout => xin_reg_i
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-- );
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-- );
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|
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-- QIN_REG: register_1b
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-- QIN_REG: register_1b
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- ce => start,
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-- ce => start,
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-- reset => reset,
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-- reset => reset,
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-- din => qin_i,
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-- din => qin_i,
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-- dout => qin_reg_i
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-- dout => qin_reg_i
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-- );
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-- );
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|
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-- CIN_REG: register_1b
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-- CIN_REG: register_1b
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- ce => start,
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-- ce => start,
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-- reset => reset,
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-- reset => reset,
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-- din => cin_i,
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-- din => cin_i,
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-- dout => cin_reg_i
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-- dout => cin_reg_i
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-- );
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-- );
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-- control
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-- control
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-- delay_1_cycle: d_flip_flop
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-- delay_1_cycle: d_flip_flop
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- reset => reset,
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-- reset => reset,
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-- din => start,
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-- din => start,
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-- dout => load_out_regs_i
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-- dout => load_out_regs_i
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-- );
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-- );
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|
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-- done_signal: d_flip_flop
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-- done_signal: d_flip_flop
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-- port map(core_clk => core_clk,
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-- port map(core_clk => core_clk,
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-- reset => reset,
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-- reset => reset,
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-- din => load_out_regs_i,
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-- din => load_out_regs_i,
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-- dout => done_i
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-- dout => done_i
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-- );
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-- );
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-- output registers
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-- output registers
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RESULT_REG: register_n
|
RESULT_REG: register_n
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generic map( n => (width+2)
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generic map( n => (width+2)
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)
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)
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port map(core_clk => core_clk,
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port map(core_clk => core_clk,
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-- ce => load_out_regs_i,
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-- ce => load_out_regs_i,
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ce => start,
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ce => start,
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reset => reset,
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reset => reset,
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din => r_i,
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din => r_i,
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dout => r_reg_i
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dout => r_reg_i
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);
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);
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