------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: operand_mem.vhd / entity operand_mem
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-- Module Name: operand_mem.vhd / entity operand_mem
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--
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--
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-- Last Modified: 18/06/2012
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-- Last Modified: 18/06/2012
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--
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--
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-- Description: BRAM memory and logic to the store 4 (1536-bit) operands and the
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-- Description: BRAM memory and logic to the store 4 (1536-bit) operands and the
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-- modulus for the montgomery multiplier
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-- modulus for the montgomery multiplier
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--
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--
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--
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--
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-- Dependencies: modulus_ram, operand_ram
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-- Dependencies: modulus_ram, operand_ram
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 2.00 - Removed y_register -> seperate module
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-- Revision 2.00 - Removed y_register -> seperate module
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-- Revision 1.01 - Added "result_dest_op" input
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-- Revision 1.01 - Added "result_dest_op" input
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity operand_mem is
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entity operand_mem is
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generic(n : integer := 1536
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generic(n : integer := 1536
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);
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);
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port(-- data interface (plb side)
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port(-- data interface (plb side)
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data_in : in std_logic_vector(31 downto 0);
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data_in : in std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(31 downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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rw_address : in std_logic_vector(8 downto 0);
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-- address structure:
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-- address structure:
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-- bit: 8 -> '1': modulus
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-- bit: 8 -> '1': modulus
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-- '0': operands
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-- '0': operands
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-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
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-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
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-- don't care in case of modulus
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-- don't care in case of modulus
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-- bits: 5-0 -> modulus_addr / operand_addr resp.
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-- bits: 5-0 -> modulus_addr / operand_addr resp.
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-- operand interface (multiplier side)
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-- operand interface (multiplier side)
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op_sel : in std_logic_vector(1 downto 0);
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op_sel : in std_logic_vector(1 downto 0);
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xy_out : out std_logic_vector(1535 downto 0);
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xy_out : out std_logic_vector(1535 downto 0);
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m : out std_logic_vector(1535 downto 0);
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m : out std_logic_vector(1535 downto 0);
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result_in : in std_logic_vector(1535 downto 0);
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result_in : in std_logic_vector(1535 downto 0);
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-- control signals
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-- control signals
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load_op : in std_logic;
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load_op : in std_logic;
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load_m : in std_logic;
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load_m : in std_logic;
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load_result : in std_logic;
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load_result : in std_logic;
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result_dest_op : in std_logic_vector(1 downto 0);
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result_dest_op : in std_logic_vector(1 downto 0);
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collision : out std_logic;
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collision : out std_logic;
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-- system clock
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-- system clock
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clk : in std_logic
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clk : in std_logic
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);
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);
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end operand_mem;
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end operand_mem;
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architecture Behavioral of operand_mem is
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architecture Behavioral of operand_mem is
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-- single port (32-bit -> 1536-bit) block ram
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-- single port (32-bit -> 1536-bit) block ram
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component modulus_ram
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component modulus_ram
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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modulus_addr : in std_logic_vector(5 downto 0);
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modulus_addr : in std_logic_vector(5 downto 0);
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write_modulus : in std_logic;
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write_modulus : in std_logic;
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modulus_in : in std_logic_vector(31 downto 0);
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modulus_in : in std_logic_vector(31 downto 0);
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modulus_out : out std_logic_vector(1535 downto 0)
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modulus_out : out std_logic_vector(1535 downto 0)
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);
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);
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end component;
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end component;
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-- dual port block ram
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-- dual port block ram
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component operand_ram
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component operand_ram
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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operand_addr : in std_logic_vector(5 downto 0);
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operand_addr : in std_logic_vector(5 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in : in std_logic_vector(31 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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operand_in_sel : in std_logic_vector(1 downto 0);
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write_operand : in std_logic;
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write_operand : in std_logic;
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operand_out_sel : in std_logic_vector(1 downto 0);
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operand_out_sel : in std_logic_vector(1 downto 0);
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result_dest_op : in std_logic_vector(1 downto 0);
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result_dest_op : in std_logic_vector(1 downto 0);
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write_result : in std_logic;
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write_result : in std_logic;
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result_in : in std_logic_vector(1535 downto 0);
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result_in : in std_logic_vector(1535 downto 0);
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collision : out std_logic;
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collision : out std_logic;
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result_out : out std_logic_vector(31 downto 0);
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result_out : out std_logic_vector(31 downto 0);
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operand_out : out std_logic_vector(1535 downto 0)
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operand_out : out std_logic_vector(1535 downto 0)
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);
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);
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end component;
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end component;
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signal xy_data_i : std_logic_vector(31 downto 0);
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signal xy_data_i : std_logic_vector(31 downto 0);
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signal xy_addr_i : std_logic_vector(5 downto 0);
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signal xy_addr_i : std_logic_vector(5 downto 0);
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signal operand_in_sel_i : std_logic_vector(1 downto 0);
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signal operand_in_sel_i : std_logic_vector(1 downto 0);
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signal collision_i : std_logic;
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signal collision_i : std_logic;
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signal xy_op_i : std_logic_vector(1535 downto 0);
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signal xy_op_i : std_logic_vector(1535 downto 0);
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signal m_addr_i : std_logic_vector(5 downto 0);
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signal m_addr_i : std_logic_vector(5 downto 0);
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signal write_m_i : std_logic;
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signal write_m_i : std_logic;
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signal m_data_i : std_logic_vector(31 downto 0);
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signal m_data_i : std_logic_vector(31 downto 0);
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begin
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begin
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-- map outputs
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-- map outputs
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xy_out <= xy_op_i;
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xy_out <= xy_op_i;
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collision <= collision_i;
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collision <= collision_i;
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-- map inputs
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-- map inputs
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xy_addr_i <= rw_address(5 downto 0);
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xy_addr_i <= rw_address(5 downto 0);
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m_addr_i <= rw_address(5 downto 0);
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m_addr_i <= rw_address(5 downto 0);
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operand_in_sel_i <= rw_address(7 downto 6);
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operand_in_sel_i <= rw_address(7 downto 6);
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xy_data_i <= data_in;
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xy_data_i <= data_in;
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m_data_i <= data_in;
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m_data_i <= data_in;
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write_m_i <= load_m;
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write_m_i <= load_m;
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-- xy operand storage
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-- xy operand storage
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xy_ram: operand_ram port map(
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xy_ram: operand_ram port map(
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clk => clk,
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clk => clk,
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collision => collision_i,
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collision => collision_i,
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operand_addr => xy_addr_i,
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operand_addr => xy_addr_i,
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operand_in => xy_data_i,
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operand_in => xy_data_i,
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operand_in_sel => operand_in_sel_i,
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operand_in_sel => operand_in_sel_i,
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result_out => data_out,
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result_out => data_out,
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write_operand => load_op,
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write_operand => load_op,
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operand_out => xy_op_i,
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operand_out => xy_op_i,
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operand_out_sel => op_sel,
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operand_out_sel => op_sel,
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result_dest_op => result_dest_op,
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result_dest_op => result_dest_op,
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write_result => load_result,
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write_result => load_result,
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result_in => result_in
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result_in => result_in
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);
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);
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-- modulus storage
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-- modulus storage
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m_ram : modulus_ram
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m_ram : modulus_ram
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port map(
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port map(
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clk => clk,
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clk => clk,
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modulus_addr => m_addr_i,
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modulus_addr => m_addr_i,
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write_modulus => write_m_i,
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write_modulus => write_m_i,
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modulus_in => m_data_i,
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modulus_in => m_data_i,
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modulus_out => m
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modulus_out => m
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);
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);
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end Behavioral;
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end Behavioral;
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