------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- Geoffrey Ottoy - DraMCo research group
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-- Geoffrey Ottoy - DraMCo research group
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--
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--
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-- Module Name: stepping_logic.vhd / entity stepping_logic
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-- Module Name: stepping_logic.vhd / entity stepping_logic
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--
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--
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-- Last Modified: 23/01/2012
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-- Last Modified: 23/01/2012
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--
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--
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-- Description: stepping logic for the pipelined montgomery multiplier
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-- Description: stepping logic for the pipelined montgomery multiplier
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--
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--
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--
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--
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-- Dependencies: counter_sync
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-- Dependencies: counter_sync
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 5.01 - defined integer range for t_sel and n_sel resulting in less LUTs
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-- Revision 5.01 - defined integer range for t_sel and n_sel resulting in less LUTs
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-- Revision 5.00 - made the reset value changeable in runtime
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-- Revision 5.00 - made the reset value changeable in runtime
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-- Revision 4.01 - Delayed ready pulse with 1 clk cylce. This delay is necessary
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-- Revision 4.01 - Delayed ready pulse with 1 clk cylce. This delay is necessary
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-- for the reduction to complete.
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-- for the reduction to complete.
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-- Revision 4.00 - Changed design to fit new pipeline-architecture
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-- Revision 4.00 - Changed design to fit new pipeline-architecture
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-- (i.e. 1 clock cycle / stage)
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-- (i.e. 1 clock cycle / stage)
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-- Revision 3.00 - Removed second delay on next_x
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-- Revision 3.00 - Removed second delay on next_x
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-- Revision 2.00 - Changed operation to give a pulse on stepping_done when pipeline
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-- Revision 2.00 - Changed operation to give a pulse on stepping_done when pipeline
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-- operation has finished
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-- operation has finished
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-- Revision 1.00 - Architecture
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-- Revision 1.00 - Architecture
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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--
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--
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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--
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--
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-- NOTICE:
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-- NOTICE:
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--
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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-- by other third parties!
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--
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--
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity stepping_logic is
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entity stepping_logic is
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generic( n : integer := 1536; -- max nr of steps required to complete a multiplication
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generic( n : integer := 1536; -- max nr of steps required to complete a multiplication
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t : integer := 192 -- total nr of steps in the pipeline
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t : integer := 192 -- total nr of steps in the pipeline
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);
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);
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port( core_clk : in STD_LOGIC;
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port( core_clk : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
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t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece
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n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
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n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication
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start_first_stage : out STD_LOGIC;
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start_first_stage : out STD_LOGIC;
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stepping_done : out STD_LOGIC
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stepping_done : out STD_LOGIC
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);
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);
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end stepping_logic;
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end stepping_logic;
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architecture Behavioral of stepping_logic is
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architecture Behavioral of stepping_logic is
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component d_flip_flop
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component d_flip_flop
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port(core_clk : in STD_LOGIC;
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port(core_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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din : in STD_LOGIC;
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din : in STD_LOGIC;
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dout : out STD_LOGIC
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dout : out STD_LOGIC
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);
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);
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end component;
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end component;
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component counter_sync
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component counter_sync
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generic(max_value : integer := 16
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generic(max_value : integer := 16
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);
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);
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port(reset_value : in integer;
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port(reset_value : in integer;
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core_clk : in STD_LOGIC;
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core_clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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ce : in STD_LOGIC;
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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overflow : out STD_LOGIC
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overflow : out STD_LOGIC
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);
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);
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end component;
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end component;
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signal laststeps_in_i : std_logic := '0';
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signal laststeps_in_i : std_logic := '0';
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signal laststeps_out_i : std_logic := '0';
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signal laststeps_out_i : std_logic := '0';
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signal start_stop_in_i : std_logic := '0';
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signal start_stop_in_i : std_logic := '0';
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signal start_stop_out_i : std_logic := '0';
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signal start_stop_out_i : std_logic := '0';
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signal steps_in_i : std_logic := '0';
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signal steps_in_i : std_logic := '0';
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signal steps_out_i : std_logic := '0';
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signal steps_out_i : std_logic := '0';
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signal substeps_in_i : std_logic := '0';
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signal substeps_in_i : std_logic := '0';
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signal substeps_out_i : std_logic := '0';
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signal substeps_out_i : std_logic := '0';
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signal done_reg_in_i : std_logic := '0';
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signal done_reg_in_i : std_logic := '0';
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signal done_reg_out_i : std_logic := '0';
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signal done_reg_out_i : std_logic := '0';
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signal start_first_stage_i : std_logic := '0';
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signal start_first_stage_i : std_logic := '0';
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signal start_i : std_logic := '0';
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signal start_i : std_logic := '0';
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begin
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begin
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start_i <= start;
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start_i <= start;
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-- map outputs
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-- map outputs
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start_first_stage <= start_first_stage_i;
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start_first_stage <= start_first_stage_i;
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stepping_done <= laststeps_out_i;
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stepping_done <= laststeps_out_i;
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-- internal signals
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-- internal signals
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start_stop_in_i <= start_i or (start_stop_out_i and not steps_out_i);
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start_stop_in_i <= start_i or (start_stop_out_i and not steps_out_i);
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substeps_in_i <= start_stop_in_i;
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substeps_in_i <= start_stop_in_i;
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steps_in_i <= substeps_out_i;
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steps_in_i <= substeps_out_i;
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done_reg_in_i <= steps_out_i or (done_reg_out_i and not laststeps_out_i);
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done_reg_in_i <= steps_out_i or (done_reg_out_i and not laststeps_out_i);
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laststeps_in_i <= done_reg_in_i;
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laststeps_in_i <= done_reg_in_i;
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start_first_stage_i <= start_i or steps_in_i;
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start_first_stage_i <= start_i or steps_in_i;
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--start_first_stage_i <= steps_in_i;
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--start_first_stage_i <= steps_in_i;
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done_reg: d_flip_flop
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done_reg: d_flip_flop
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port map(core_clk => core_clk,
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port map(core_clk => core_clk,
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reset => reset,
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reset => reset,
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din => done_reg_in_i,
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din => done_reg_in_i,
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dout => done_reg_out_i
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dout => done_reg_out_i
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);
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);
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start_stop_reg: d_flip_flop
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start_stop_reg: d_flip_flop
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port map(core_clk => core_clk,
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port map(core_clk => core_clk,
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reset => reset,
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reset => reset,
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din => start_stop_in_i,
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din => start_stop_in_i,
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dout => start_stop_out_i
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dout => start_stop_out_i
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);
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);
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-- for counting the last steps
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-- for counting the last steps
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laststeps_counter: counter_sync
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laststeps_counter: counter_sync
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generic map(max_value => t
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generic map(max_value => t
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)
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)
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port map(reset_value => t_sel,
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port map(reset_value => t_sel,
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core_clk => core_clk,
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core_clk => core_clk,
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ce => laststeps_in_i,
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ce => laststeps_in_i,
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reset => reset,
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reset => reset,
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overflow => laststeps_out_i
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overflow => laststeps_out_i
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);
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);
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-- counter for keeping track of the steps
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-- counter for keeping track of the steps
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steps_counter: counter_sync
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steps_counter: counter_sync
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generic map(max_value => n
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generic map(max_value => n
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)
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)
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port map(reset_value => (n_sel),
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port map(reset_value => (n_sel),
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core_clk => core_clk,
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core_clk => core_clk,
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ce => steps_in_i,
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ce => steps_in_i,
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reset => reset,
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reset => reset,
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overflow => steps_out_i
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overflow => steps_out_i
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);
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);
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-- makes sure we don't start too early with a new step
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-- makes sure we don't start too early with a new step
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substeps_counter: counter_sync
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substeps_counter: counter_sync
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generic map(max_value => 2
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generic map(max_value => 2
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)
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)
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port map(reset_value => 2,
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port map(reset_value => 2,
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core_clk => core_clk,
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core_clk => core_clk,
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ce => substeps_in_i,
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ce => substeps_in_i,
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reset => reset,
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reset => reset,
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overflow => substeps_out_i
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overflow => substeps_out_i
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);
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);
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