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----------------------------------------------------------------------
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---- cel_1b ----
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---- cell_1b ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- 1-bit cell for use in the montgommery multiplier systolic ----
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---- 1-bit cell for use in the montgommery multiplier systolic ----
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---- array ----
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---- array ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - cell_1bit_adder ----
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---- - cell_1bit_adder ----
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---- - cell_1bit_mux ----
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---- - cell_1bit_mux ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- 1-bit cell for the systolic array
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-- 1-bit cell for the systolic array
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entity cell_1b is
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entity cell_1b is
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port (
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port (
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-- operand input bits (m+y, y and m)
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-- operand input bits (m+y, y and m)
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my : in std_logic;
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my : in std_logic;
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y : in std_logic;
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y : in std_logic;
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m : in std_logic;
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m : in std_logic;
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-- operand x input bit and q (serial)
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-- operand x input bit and q
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x : in std_logic;
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x : in std_logic;
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q : in std_logic;
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q : in std_logic;
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-- previous result input bit
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-- previous result input bit
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a : in std_logic;
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a : in std_logic;
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-- carry's
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-- carry's
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cin : in std_logic;
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cin : in std_logic;
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cout : out std_logic;
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cout : out std_logic;
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-- cell result out
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-- cell result out
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r : out std_logic
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r : out std_logic
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);
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);
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end cell_1b;
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end cell_1b;
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architecture Structural of cell_1b is
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architecture Structural of cell_1b is
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-- mux to adder connection
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-- mux to adder connection
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signal mux2adder : std_logic;
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signal mux2adder : std_logic;
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begin
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begin
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-- mux for my, y and m input bits
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-- mux for my, y and m input bits
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cell_mux : cell_1b_mux
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cell_mux : cell_1b_mux
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port map(
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port map(
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my => my,
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my => my,
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y => y,
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y => y,
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m => m,
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m => m,
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x => x,
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x => x,
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q => q,
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q => q,
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result => mux2adder
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result => mux2adder
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);
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);
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-- full adder for a+mux2adder
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-- full adder for a+mux2adder
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cell_adder : cell_1b_adder
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cell_adder : cell_1b_adder
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port map(
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port map(
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a => a,
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a => a,
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b => mux2adder,
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b => mux2adder,
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cin => cin,
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cin => cin,
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cout => cout,
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cout => cout,
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r => r
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r => r
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);
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);
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end Structural;
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end Structural;
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