----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- modulus_ram_gen ----
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---- modulus_ram_gen ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- BRAM memory and logic to store the modulus, due to the ----
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---- BRAM memory and logic to store the modulus, due to the ----
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---- achitecture, a minimum depth of 2 is needed for this ----
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---- achitecture, a minimum depth of 2 is needed for this ----
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---- module to be inferred into blockram ----
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---- module to be inferred into blockram ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - dpram_generic ----
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---- - dpram_generic ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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use mod_sim_exp.std_functions.all;
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-- behavorial description of a RAM to hold the modulus, with
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-- behavorial description of a RAM to hold the modulus, with
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-- adjustable width and depth(nr of moduluses)
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-- adjustable width and depth(nr of moduluses)
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entity modulus_ram_gen is
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entity modulus_ram_gen is
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generic(
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generic(
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width : integer := 1536; -- must be a multiple of 32
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width : integer := 1536; -- must be a multiple of 32
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depth : integer := 2 -- nr of moduluses
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depth : integer := 2 -- nr of moduluses
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);
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);
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port(
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port(
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clk : in std_logic;
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-- bus side
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-- bus side
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bus_clk : in std_logic;
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write_modulus : in std_logic; -- write enable
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write_modulus : in std_logic; -- write enable
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_addr : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_in : in std_logic_vector(31 downto 0); -- modulus word data in
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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modulus_sel : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
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-- multiplier side
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-- multiplier side
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core_clk : in std_logic;
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modulus_out : out std_logic_vector(width-1 downto 0)
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modulus_out : out std_logic_vector(width-1 downto 0)
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);
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);
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end modulus_ram_gen;
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end modulus_ram_gen;
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architecture Behavioral of modulus_ram_gen is
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architecture Behavioral of modulus_ram_gen is
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--- constants
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--- constants
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constant nrRAMs : integer := width/32;
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constant nrRAMs : integer := width/32;
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constant RAMselect_aw : integer := log2(nrRAMs);
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constant RAMselect_aw : integer := log2(nrRAMs);
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constant RAMdepth_aw : integer := log2(depth);
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constant RAMdepth_aw : integer := log2(depth);
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constant total_aw : integer := RAMdepth_aw+RAMselect_aw;
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constant total_aw : integer := RAMdepth_aw+RAMselect_aw;
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-- interconnection signals
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-- interconnection signals
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signal modulus_rdaddr : std_logic_vector(RAMdepth_aw-1 downto 0);
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signal modulus_rdaddr : std_logic_vector(RAMdepth_aw-1 downto 0);
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signal modulus_wraddr : std_logic_vector(total_aw-1 downto 0);
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signal modulus_wraddr : std_logic_vector(total_aw-1 downto 0);
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signal we : std_logic_vector(nrRAMs-1 downto 0);
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signal we : std_logic_vector(nrRAMs-1 downto 0);
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begin
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begin
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modulus_wraddr(RAMselect_aw-1 downto 0) <= modulus_addr;
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modulus_wraddr(RAMselect_aw-1 downto 0) <= modulus_addr;
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modulus_wraddr(total_aw-1 downto RAMselect_aw) <= modulus_in_sel;
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modulus_wraddr(total_aw-1 downto RAMselect_aw) <= modulus_in_sel;
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-- generate (width/32) blocks of 32-bit ram with a given depth
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-- generate (width/32) blocks of 32-bit ram with a given depth
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-- these rams outputs are concatenated to a width-bit signal
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-- these rams outputs are concatenated to a width-bit signal
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ramblocks : for i in 0 to nrRAMs-1 generate
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ramblocks : for i in 0 to nrRAMs-1 generate
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ramblock: dpram_generic
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ramblock: dpram_generic
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generic map(
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generic map(
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depth => depth
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depth => depth
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)
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)
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port map(
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port map(
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clk => clk,
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-- write port
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-- write port
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waddr => modulus_wraddr(total_aw-1 downto RAMselect_aw),
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clkA => bus_clk,
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we => we(i),
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waddrA => modulus_wraddr(total_aw-1 downto RAMselect_aw),
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din => modulus_in,
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weA => we(i),
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dinA => modulus_in,
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-- read port
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-- read port
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raddr => modulus_rdaddr,
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clkB => core_clk,
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dout => modulus_out(((i+1)*32)-1 downto i*32)
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raddrB => modulus_rdaddr,
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doutB => modulus_out(((i+1)*32)-1 downto i*32)
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);
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);
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-- connect the w
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-- connect the w
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process (write_modulus, modulus_wraddr)
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process (write_modulus, modulus_wraddr)
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begin
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begin
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if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
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if modulus_wraddr(RAMselect_aw-1 downto 0) = conv_std_logic_vector(i,RAMselect_aw) then
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we(i) <= write_modulus;
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we(i) <= write_modulus;
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else
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else
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we(i) <= '0';
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we(i) <= '0';
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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modulus_rdaddr <= modulus_sel;
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modulus_rdaddr <= modulus_sel;
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end Behavioral;
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end Behavioral;
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