----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- mont_multiplier ----
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---- mont_multiplier ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- n-bit montgomery multiplier with a pipelined systolic ----
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---- n-bit montgomery multiplier with a pipelined systolic ----
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---- array ----
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---- array ----
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---- ----
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---- ----
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---- Dependencies: ----
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---- Dependencies: ----
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---- - x_shift_reg ----
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---- - x_shift_reg ----
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---- - adder_n ----
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---- - adder_n ----
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---- - d_flip_flop ----
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---- - d_flip_flop ----
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---- - sys_pipeline ----
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---- - sys_pipeline ----
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---- - cell_1b_adder ----
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---- - cell_1b_adder ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- Structural description of the montgommery multiply pipeline
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-- Structural description of the montgommery multiply pipeline
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-- contains the x operand shift register, my adder, the pipeline and
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-- contains the x operand shift register, my adder, the pipeline and
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-- reduction adder. To do a multiplication, the following actions must take place:
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-- reduction adder. To do a multiplication, the following actions must take place:
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--
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--
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-- * load in the x operand in the shift register using the xy bus and load_x
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-- * load in the x operand in the shift register using the xy bus and load_x
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-- * place the y operand on the xy bus for the rest of the operation
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-- * place the y operand on the xy bus for the rest of the operation
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-- * generate a start pulse of 1 clk cycle long on start
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-- * generate a start pulse of 1 clk cycle long on start
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-- * wait for ready signal
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-- * wait for ready signal
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-- * result is avaiable on the r bus
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-- * result is avaiable on the r bus
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--
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--
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entity mont_multiplier is
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entity mont_multiplier is
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generic (
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generic (
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n : integer := 1536; -- width of the operands
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n : integer := 1536; -- width of the operands
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nr_stages : integer := 96; -- total number of stages
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t : integer := 96; -- total number of stages (minimum 2)
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stages_low : integer := 32 -- lower number of stages
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tl : integer := 32; -- lower number of stages (minimum 1)
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split : boolean := true -- if true the pipeline wil be split in 2 parts,
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-- if false there are no lower stages, only t counts
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);
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);
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port (
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port (
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-- clock input
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-- clock input
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core_clk : in std_logic;
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core_clk : in std_logic;
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-- operand inputs
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-- operand inputs
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xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
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xy : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
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m : in std_logic_vector((n-1) downto 0); -- modulus
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m : in std_logic_vector((n-1) downto 0); -- modulus
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-- result output
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-- result output
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r : out std_logic_vector((n-1) downto 0); -- result
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r : out std_logic_vector((n-1) downto 0); -- result
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-- control signals
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-- control signals
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start : in std_logic;
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start : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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p_sel : in std_logic_vector(1 downto 0);
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p_sel : in std_logic_vector(1 downto 0);
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load_x : in std_logic;
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load_x : in std_logic;
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ready : out std_logic
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ready : out std_logic
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);
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);
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end mont_multiplier;
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end mont_multiplier;
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architecture Structural of mont_multiplier is
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architecture Structural of mont_multiplier is
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constant t : integer := nr_stages;
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constant s : integer := n/t; -- stage width (# bits)
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constant tl : integer := stages_low;
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constant s : integer := n/nr_stages; -- stage width (# bits)
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constant nl : integer := s*tl; -- lower pipeline width (# bits)
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constant nl : integer := s*tl; -- lower pipeline width (# bits)
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constant nh : integer := n - nl; -- higher pipeline width (# bits)
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constant nh : integer := n - nl; -- higher pipeline width (# bits)
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signal reset_multiplier : std_logic;
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signal reset_multiplier : std_logic;
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signal start_multiplier : std_logic;
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signal start_multiplier : std_logic;
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signal p_sel_i : std_logic_vector(1 downto 0);
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signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part
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signal t_sel : integer range 0 to t; -- width in stages of selected pipeline part
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signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part
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signal n_sel : integer range 0 to n; -- width in bits of selected pipeline part
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signal next_xi : std_logic;
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signal next_xi : std_logic;
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signal xi : std_logic;
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signal xi : std_logic;
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signal start_first_stage : std_logic;
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signal start_first_stage : std_logic;
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begin
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begin
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-- multiplier is reset every calculation or reset
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-- multiplier is reset every calculation or reset
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reset_multiplier <= reset or start;
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reset_multiplier <= reset or start;
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-- start is delayed 1 cycle
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-- start is delayed 1 cycle
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delay_1_cycle : d_flip_flop
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delay_1_cycle : d_flip_flop
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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reset => reset,
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reset => reset,
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din => start,
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din => start,
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dout => start_multiplier
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dout => start_multiplier
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);
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);
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-- register to store the x value in
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-- register to store the x value in
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-- outputs the operand in serial using a shift register
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-- outputs the operand in serial using a shift register
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x_selection : x_shift_reg
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x_selection : x_shift_reg
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generic map(
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generic map(
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n => n,
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n => n,
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t => nr_stages,
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t => t,
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tl => stages_low
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tl => tl
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)
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)
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port map(
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port map(
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clk => core_clk,
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clk => core_clk,
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reset => reset,
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reset => reset,
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x_in => xy,
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x_in => xy,
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load_x => load_x,
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load_x => load_x,
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next_x => next_xi,
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next_x => next_xi,
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p_sel => p_sel,
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p_sel => p_sel_i,
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xi => xi
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xi => xi
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);
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);
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----------------------------------------
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-- SINGLE PIPELINE ASSIGNMENTS
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----------------------------------------
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single_pipeline : if split=false generate
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p_sel_i <= "11";
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t_sel <= t;
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n_sel <= n-1;
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end generate;
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----------------------------------------
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-- SPLIT PIPELINE ASSIGNMENTS
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----------------------------------------
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split_pipeline : if split=true generate
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-- this module controls the pipeline operation
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-- this module controls the pipeline operation
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-- width in stages for selected pipeline
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-- width in stages for selected pipeline
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with p_sel select
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with p_sel select
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t_sel <= tl when "01", -- lower pipeline part
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t_sel <= tl when "01", -- lower pipeline part
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t-tl when "10", -- higher pipeline part
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t-tl when "10", -- higher pipeline part
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t when others; -- full pipeline
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t when others; -- full pipeline
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-- width in bits for selected pipeline
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-- width in bits for selected pipeline
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with p_sel select
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with p_sel select
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n_sel <= nl-1 when "01", -- lower pipeline part
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n_sel <= nl-1 when "01", -- lower pipeline part
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nh-1 when "10", -- higher pipeline part
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nh-1 when "10", -- higher pipeline part
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n-1 when others; -- full pipeline
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n-1 when others; -- full pipeline
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p_sel_i <= p_sel;
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end generate;
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-- stepping control logic to keep track off the multiplication and when it is done
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-- stepping control logic to keep track off the multiplication and when it is done
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stepping_control : stepping_logic
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stepping_control : stepping_logic
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generic map(
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generic map(
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n => n, -- max nr of steps required to complete a multiplication
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n => n, -- max nr of steps required to complete a multiplication
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t => nr_stages -- total nr of steps in the pipeline
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t => t -- total nr of steps in the pipeline
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)
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)
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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start => start_multiplier,
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start => start_multiplier,
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reset => reset_multiplier,
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reset => reset_multiplier,
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t_sel => t_sel,
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t_sel => t_sel,
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n_sel => n_sel,
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n_sel => n_sel,
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start_first_stage => start_first_stage,
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start_first_stage => start_first_stage,
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stepping_done => ready
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stepping_done => ready
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);
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);
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systolic_array : sys_pipeline
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systolic_array : sys_pipeline
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generic map(
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generic map(
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n => n,
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n => n,
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t => nr_stages,
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t => t,
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tl => stages_low
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tl => tl,
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split => split
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)
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)
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port map(
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port map(
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core_clk => core_clk,
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core_clk => core_clk,
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y => xy,
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y => xy,
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m => m,
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m => m,
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xi => xi,
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xi => xi,
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next_x => next_xi,
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next_x => next_xi,
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start => start_first_stage,
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start => start_first_stage,
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reset => reset_multiplier,
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reset => reset_multiplier,
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p_sel => p_sel,
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p_sel => p_sel_i,
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r => r
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r => r
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);
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);
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end Structural;
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end Structural;
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No newline at end of file
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No newline at end of file
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