-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: channel_selector.vhd
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--| File: ctrl_channel_selector.vhd
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--| Version: 0.2
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--| Version: 0.3
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Channel Selector
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--| CONTROL - Channel Selector
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--| This controls the comunication with the daq module.
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--| This controls the comunication with the daq module.
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jul-2009 | First testing
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--| 0.1 | jul-2009 | First testing
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--| 0.2 | jul-2009 | Added generic number of channel
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--| 0.2 | jul-2009 | Added generic number of channel
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--| 0.3 | jul-2009 | Added signal indicating when it's selecting the first channel
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TODO
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-- TODO
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-- · Speed up the design
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-- · Speed up...
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-- · Generic width in channel_number_O
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.math_real.all;
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use ieee.math_real.all;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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entity channel_selector is
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entity ctrl_channel_selector is
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generic(
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generic(
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N_CHANNELS: integer := 16 -- number of channels
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CHANNEL_WIDTH: integer := 4 -- number of channels 2**CHANNEL_WIDTH, max. 4
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);
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);
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port(
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port(
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channels_I: in std_logic_vector(N_CHANNELS-1 downto 0);
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channels_I: in std_logic_vector(integer(2**real(CHANNEL_WIDTH))-1 downto 0);
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channel_number_O: out std_logic_vector(3 downto 0);
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channel_number_O: out std_logic_vector(3 downto 0);
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first_channel_O: out std_logic;
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clk_I: in std_logic;
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clk_I: in std_logic;
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enable_I: in std_logic;
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enable_I: in std_logic;
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reset_I: in std_logic
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reset_I: in std_logic
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);
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);
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end entity channel_selector;
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end entity channel_selector;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH01 of channel_selector is
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architecture ARCH01 of ctrl_channel_selector is
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constant CHANNEL_WIDTH: integer := integer(ceil(log2(real(N_CHANNELS))));
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constant N_CHANNELS: integer := integer(2**real(CHANNEL_WIDTH));
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-- signal channel: unsigned(CHANNEL_WIDTH-1 downto 0);
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-- signal next_channel: unsigned(CHANNEL_WIDTH-1 downto 0);
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-- signal next_is_first_channel: std_logic;
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signal channel: unsigned(CHANNEL_WIDTH-1 downto 0);
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signal channel: unsigned(CHANNEL_WIDTH-1 downto 0);
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signal next_channel: unsigned(CHANNEL_WIDTH-1 downto 0);
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signal next_channel: unsigned(CHANNEL_WIDTH downto 0);
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signal next_is_first_channel: std_logic;
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signal rotated: unsigned(N_CHANNELS-1 downto 0);
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signal plus: unsigned(CHANNEL_WIDTH downto 0);
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Output
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-- Output
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channel_number_O <= (3 downto CHANNEL_WIDTH => '0') & std_logic_vector(channel);
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channel_number_O <= (3 downto CHANNEL_WIDTH => '0') & std_logic_vector(channel);
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--channel_number_O <= std_logic_vector(channel);
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--channel_number_O <= std_logic_vector(channel);
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Combinational selection
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-- Combinational selection of next channel
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P_comb: process(channel,channels_I)
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variable j : integer range 0 to N_CHANNELS-1;
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variable index: integer range 0 to N_CHANNELS-1;
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begin
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-- P_comb: process(channel,channels_I)
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-- variable j : integer range 0 to N_CHANNELS-1;
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-- variable index: integer range 0 to N_CHANNELS-1;
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-- begin
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-- for j in 0 to N_CHANNELS-1 loop
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-- if (j + to_integer(channel) + 1) > (N_CHANNELS - 1) then
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-- index := j + to_integer(channel) + 1 - N_CHANNELS;
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-- next_is_first_channel <= '1';
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-- else
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-- index := j + to_integer(channel) + 1;
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-- next_is_first_channel <= '0';
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-- end if;
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-- -- for i in 0 to N_CHANNELS loop
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-- if channels_I(index) = '1' then
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-- if i = to_integer(channel) then
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-- next_channel <= to_unsigned(index, CHANNEL_WIDTH);
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-- exit;
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-- exit;
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-- else
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-- next_channel <= channel;
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-- end if;
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-- end if;
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-- end loop;
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-- end loop;
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-- end process;
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-- for i in 0 to N_CHANNELS loop
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--100.0 MHz 67.1 MHz (N_CHANNELS = 16)
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--i := to_natural(channel);
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-- 271 of 38400 (1%)
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for j in 0 to N_CHANNELS-1 loop
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if (j + to_integer(channel) + 1) > (N_CHANNELS - 1) then
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index := j + to_integer(channel) + 1 - N_CHANNELS;
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else
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index := j + to_integer(channel) + 1;
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end if;
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if channels_I(index) = '1' then
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next_channel <= to_unsigned(index, CHANNEL_WIDTH);
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rotated <= unsigned(channels_I) ror (to_integer(channel));
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next_channel <= ('0' & channel) + plus;
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--next_channel <= channel + plus;
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next_is_first_channel <= next_channel (CHANNEL_WIDTH);
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P_coder: process(rotated)
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variable i: integer range 1 to N_CHANNELS-1;
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begin
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for i in 1 to N_CHANNELS-1 loop
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if rotated(i) = '1' then
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plus <= to_unsigned(i, CHANNEL_WIDTH+1);
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exit;
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exit;
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else
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else
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next_channel <= channel;
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plus <= (CHANNEL_WIDTH =>'1') & (CHANNEL_WIDTH - 1 downto 0 => '0');
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end if;
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end if;
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end loop;
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end loop;
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end process;
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--100.0 MHz 70.6 MHz (N_CHANNELS = 16)
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-- 137 of 38400 (0%)
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--------------------------------------------------------------------------------------------------
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-- Clocked selection of actual channel
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-- P_clock: process(enable_I, reset_I, next_channel, clk_I)
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-- begin
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-- if clk_I'event and clk_I = '1' then
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-- if reset_I = '1' then
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-- for i in 0 to N_CHANNELS loop
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-- channel <= (others => '0');
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-- if channel = to_unsigned(i, 4) then
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-- first_channel_O <= '1';
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-- for j in i+1 to (2*N_CHANNELS)-1 loop
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-- elsif enable_I = '1' then
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-- if j > N_CHANNELS-1 then
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-- channel <= next_channel;
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-- index := j - N_CHANNELS;
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-- first_channel_O <= next_is_first_channel;
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-- else
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-- index := j;
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-- end if;
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-- end if;
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--
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-- if channels_I(index) = '1' then
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-- next_channel <= to_unsigned(index, CHANNEL_WIDTH);
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-- exit;
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-- else
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-- next_channel <= channel;
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-- end if;
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-- end if;
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-- end loop;
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-- end process;
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-- exit;
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-- else
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-- next_channel <= channel;
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-- end if;
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-- end loop;
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end process;
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--------------------------------------------------------------------------------------------------
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-- Clocked
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P_clock: process(enable_I, reset_I, next_channel, clk_I)
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P_clock: process(enable_I, reset_I, next_channel, clk_I)
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begin
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begin
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if clk_I'event and clk_I = '1' then
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if clk_I'event and clk_I = '1' then
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if reset_I = '1' then
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if reset_I = '1' then
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channel <= (others => '0');
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channel <= (others => '0');
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first_channel_O <= '1';
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elsif enable_I = '1' then
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elsif enable_I = '1' then
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channel <= next_channel;
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channel <= next_channel(CHANNEL_WIDTH-1 downto 0);
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first_channel_O <= next_is_first_channel;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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