-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: memory_writer.vhd
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--| File: memory_writer.vhd
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--| Version: 0.1
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--| Version: 0.1
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--| Tested in: Actel A3PE1500
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| CONTROL - Memory writer
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--| CONTROL - Memory writer
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--| Read data and write it in a memory (it's a simple wishbone bridge)
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--| Read data and write it in a memory (it's a simple wishbone bridge)
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.1 | jul-2009 | First release
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--| 0.1 | jul-2009 | First release
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2009, Facundo Aguilera.
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TODO
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-- TODO
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-- · ...
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-- · ...
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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entity memory_writer is
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entity memory_writer is
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generic(
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generic(
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MEM_ADD_WIDTH: integer := 14
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MEM_ADD_WIDTH: integer := 14
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);
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);
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port(
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port(
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- to memory
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-- to memory
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DAT_O_mem: out std_logic_vector (15 downto 0);
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DAT_O_mem: out std_logic_vector (15 downto 0);
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ADR_O_mem: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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ADR_O_mem: out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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CYC_O_mem: out std_logic;
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CYC_O_mem: out std_logic;
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STB_O_mem: out std_logic;
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STB_O_mem: out std_logic;
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ACK_I_mem: in std_logic ;
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ACK_I_mem: in std_logic ;
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WE_O_mem: out std_logic;
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WE_O_mem: out std_logic;
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- to acquistion module
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-- to acquistion module
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DAT_I_adc: in std_logic_vector (15 downto 0);
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DAT_I_adc: in std_logic_vector (15 downto 0);
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-- Using an address generator, commented
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-- Using an address generator, commented
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-- ADR_O_adc: out std_logic_vector (ADC_ADD_WIDTH - 1 downto 0);
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-- ADR_O_adc: out std_logic_vector (ADC_ADD_WIDTH - 1 downto 0);
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CYC_O_adc: out std_logic;
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CYC_O_adc: out std_logic;
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STB_O_adc: out std_logic;
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STB_O_adc: out std_logic;
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ACK_I_adc: in std_logic ;
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ACK_I_adc: in std_logic ;
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WE_O_adc: out std_logic;
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WE_O_adc: out std_logic;
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- Common signals
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-- Common signals
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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-- Internal
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-- Internal
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-- reset counter(memory address) to 0
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-- reset counter(memory address) to 0
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reset_I: in std_logic;
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reset_I: in std_logic;
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-- read in clk edge from the actual address ('0' means pause, '1' means continue)
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-- read in clk edge from the actual address ('0' means pause, '1' means continue)
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enable_I: in std_logic;
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enable_I: in std_logic;
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-- buffer starts and ends here
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-- buffer starts and ends here
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-- when the buffer arrives here, address is changed to 0 (buffer size)
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-- when the buffer arrives here, address is changed to 0 (buffer size)
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final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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final_address_I: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- address wich is being writed by control
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-- address wich is being writed by control
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-- stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- stop_address: in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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-- it is set when communication ends and remains until next restart or actual address change
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-- it is set when communication ends and remains until next restart or actual address change
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finished_O: out std_logic;
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finished_O: out std_logic;
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-- When counter finishes, restart
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-- When counter finishes, restart
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continuous_I: in std_logic;
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continuous_I: in std_logic;
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);
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);
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end entity memory_writer;
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end entity memory_writer;
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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architecture ARCH11 of output_manager is
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architecture ARCH11 of output_manager is
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type DataStatusType is (
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type DataStatusType is (
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INIT,
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INIT,
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WORKING
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WORKING
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);
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);
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signal data_status: DataStatusType; -- comunicates status between both ports
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signal data_status: DataStatusType; -- comunicates status between both ports
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signal count: std_logic_vector(MEM_ADD_WIDTH-1 downto 0);
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signal count: std_logic_vector(MEM_ADD_WIDTH-1 downto 0);
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signal enable_count:std_logic;
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signal enable_count:std_logic;
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signal reset_count: std_logic;
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signal reset_count: std_logic;
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signal data: std_logic_vector(15 downto 0);
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signal data: std_logic_vector(15 downto 0);
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal s_finished, s_STB_adc, s_STB_mem: std_logic; -- previous to outputs
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signal s_finished, s_STB_adc, s_STB_mem: std_logic; -- previous to outputs
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Instantiations
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-- Instantiations
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U_COUNTER0: generic_counter
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U_COUNTER0: generic_counter
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generic map(
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generic map(
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OUTPUT_WIDTH => MEM_ADD_WIDTH -- Output width for counter.
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OUTPUT_WIDTH => MEM_ADD_WIDTH -- Output width for counter.
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)
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)
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port map(
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port map(
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clk_I => CLK_I,
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clk_I => CLK_I,
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count_O => count,
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count_O => count,
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reset_I => reset_count,
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reset_I => reset_count,
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enable_I => enable_count
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enable_I => enable_count
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);
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);
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Combinational
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-- Combinational
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-- counter
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-- counter
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s_finished <= '1' when count >= final_address_I;
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s_finished <= '1' when count >= final_address_I;
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enable_count <= '1' when enable_I = '1' and
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enable_count <= '1' when enable_I = '1' and
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data_status = WORKING and
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data_status = WORKING and
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s_STB_mem = '1' and
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s_STB_mem = '1' and
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ACK_I_mem = '1' and
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ACK_I_mem = '1' and
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s_finished = '0'
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s_finished = '0'
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else
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else
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'0';
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'0';
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reset_count <= '1' when reset_I = '1' or (s_finished = '1' and continuous_I = '1') else
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reset_count <= '1' when reset_I = '1' or (s_finished = '1' and continuous_I = '1') else
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'0';
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'0';
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-- outputs
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-- outputs
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finished_O <= s_finished;
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finished_O <= s_finished;
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STB_O_adc <= s_STB_adc;
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STB_O_adc <= s_STB_adc;
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STB_O_mem <= s_STB_mem;
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STB_O_mem <= s_STB_mem;
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DAT_O_mem <= data;
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DAT_O_mem <= data;
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ADR_O_mem <= count;
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ADR_O_mem <= count;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Clocked
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-- Clocked
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-- Lock interface when working
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-- Lock interface when working
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P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)
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P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)
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begin
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begin
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if CLK_I'event and CLK_I = '1' then
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if CLK_I'event and CLK_I = '1' then
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if enable_I /= '1' or reset_I = '1' then
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if enable_I /= '1' or reset_I = '1' then
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CYC_O_adc <= '0'; CYC_O_mem <= '0';
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CYC_O_adc <= '0'; CYC_O_mem <= '0';
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else
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else
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CYC_O_adc <= '1'; CYC_O_mem <= '1';
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CYC_O_adc <= '1'; CYC_O_mem <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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P_stb_signals: process (CLK_I, reset_I, data_status, s_STB_adc, s_STB_mem, ACK_I_adc, ACK_I_mem)
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P_stb_signals: process (CLK_I, reset_I, data_status, s_STB_adc, s_STB_mem, ACK_I_adc, ACK_I_mem)
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begin
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begin
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if CLK_I'event and CLK_I = '1' then
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if CLK_I'event and CLK_I = '1' then
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if reset_I = '1' then
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if reset_I = '1' then
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data_status <= INIT;
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data_status <= INIT;
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s_STB_adc <= '0';
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s_STB_adc <= '0';
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s_STB_mem <= '0';
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s_STB_mem <= '0';
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data <= (others => '0');
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data <= (others => '0');
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elsif enable_I = '1' then
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elsif enable_I = '1' then
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if data_status = INIT and s_STB_adc = '0' or s_STB_mem = '0' then
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if data_status = INIT and s_STB_adc = '0' or s_STB_mem = '0' then
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-- this state is only necessary when there are adc convertions in every clock
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-- this state is only necessary when there are adc convertions in every clock
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-- (for the first convertion)
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-- (for the first convertion)
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s_STB_adc <= '1';
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s_STB_adc <= '1';
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s_STB_mem <= '1';
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s_STB_mem <= '1';
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else
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else
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data_status <= WORKING;
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data_status <= WORKING;
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if s_STB_adc = '1' and ACK_I_adc = '1' then
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if s_STB_adc = '1' and ACK_I_adc = '1' then
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s_STB_mem <= '1'; -- strobe when adc ack
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s_STB_mem <= '1'; -- strobe when adc ack
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data <= DAT_I_adc; -- save data
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data <= DAT_I_adc; -- save data
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elsif s_STB_mem = '1' and ACK_I_mem = '1' then
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elsif s_STB_mem = '1' and ACK_I_mem = '1' then
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s_STB_mem <= '0';
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s_STB_mem <= '0';
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end if;
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end if;
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if s_STB_mem = '1' and ACK_I_mem = '1' then
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if s_STB_mem = '1' and ACK_I_mem = '1' then
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s_STB_adc <= '1'; -- strobe when mem ack
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s_STB_adc <= '1'; -- strobe when mem ack
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elsif s_STB_adc = '1' and ACK_I_adc = '1' then
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elsif s_STB_adc = '1' and ACK_I_adc = '1' then
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s_STB_adc <= '0';
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s_STB_adc <= '0';
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end if;
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end if;
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end if;
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end if;
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else
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else
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s_STB_adc <= '0';
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s_STB_adc <= '0';
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s_STB_mem <= '0';
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s_STB_mem <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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