----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: eppwbn_16 bit.vhd
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--| File: eppwbn_16 bit.vhd
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--| Version: 0.01
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--| Version: 0.01
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--| Tested in: Actel APA300
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--| Tested in: Actel APA300
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| The top module for 16 bit wisbone data bus.
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--| The top module for 16 bit wisbone data bus.
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | dic-2008 | First release
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--| 0.01 | dic-2008 | First release
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2009, Facundo Aguilera.
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--| Copyright ® 2009, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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--| Wishbone Rev. B.3 compatible
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--| Wishbone Rev. B.3 compatible
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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-- Bloque completo 16 bit
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-- Bloque completo 16 bit
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use work.eppwbn_pkg.all;
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use work.eppwbn_pkg.all;
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|
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entity eppwbn_16bit is
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entity eppwbn_16bit is
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port(
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port(
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-- Externo
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-- Externo
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nStrobe: in std_logic; -- HostClk/nWrite
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nStrobe: in std_logic; -- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select)
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Sel: out std_logic; -- XFlag (Select)
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- Interno
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-- Interno
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (15 downto 0);
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DAT_I: in std_logic_vector (15 downto 0);
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DAT_O: out std_logic_vector (15 downto 0);
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DAT_O: out std_logic_vector (15 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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ADR_O: out std_logic_vector (7 downto 0);
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CYC_O: out std_logic;
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CYC_O: out std_logic;
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STB_O: out std_logic;
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STB_O: out std_logic;
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ACK_I: in std_logic ;
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ACK_I: in std_logic ;
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WE_O: out std_logic
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WE_O: out std_logic
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-- TEMPORAL monitores
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-- TEMPORAL monitores
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--epp_mode_monitor: out std_logic_vector(1 downto 0)
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--epp_mode_monitor: out std_logic_vector(1 downto 0)
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);
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);
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end eppwbn_16bit;
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end eppwbn_16bit;
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architecture structural of eppwbn_16bit is
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architecture structural of eppwbn_16bit is
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-- Señales
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-- Señales
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signal s_DAT_I: std_logic_vector (7 downto 0);
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signal s_DAT_I: std_logic_vector (7 downto 0);
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signal s_DAT_O: std_logic_vector (7 downto 0);
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signal s_DAT_O: std_logic_vector (7 downto 0);
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signal s_ADR_O: std_logic_vector (7 downto 0);
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signal s_ADR_O: std_logic_vector (7 downto 0);
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signal s_CYC_O: std_logic;
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signal s_CYC_O: std_logic;
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signal s_STB_O: std_logic;
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signal s_STB_O: std_logic;
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signal s_ACK_I: std_logic;
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signal s_ACK_I: std_logic;
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signal s_WE_O: std_logic;
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signal s_WE_O: std_logic;
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begin
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begin
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U_EPPWBN8: eppwbn
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U_EPPWBN8: eppwbn
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port map(
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port map(
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-- TEMPORAL
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-- TEMPORAL
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--epp_mode_monitor => epp_mode_monitor,
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--epp_mode_monitor => epp_mode_monitor,
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-- To EPP interface
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-- To EPP interface
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nStrobe => nStrobe,
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nStrobe => nStrobe,
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Data => Data,
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Data => Data,
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nAck => nAck,
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nAck => nAck,
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busy => busy,
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busy => busy,
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PError => PError,
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PError => PError,
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Sel => Sel,
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Sel => Sel,
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nAutoFd => nAutoFd,
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nAutoFd => nAutoFd,
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PeriphLogicH => PeriphLogicH,
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PeriphLogicH => PeriphLogicH,
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nInit => nInit,
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nInit => nInit,
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nFault => nFault,
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nFault => nFault,
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nSelectIn => nSelectIn,
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nSelectIn => nSelectIn,
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-- Common signals
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-- Common signals
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RST_I => RST_I,
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RST_I => RST_I,
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CLK_I => CLK_I,
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CLK_I => CLK_I,
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-- Master EPP to slave width exteneder
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-- Master EPP to slave width exteneder
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DAT_I => s_DAT_I,
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DAT_I => s_DAT_I,
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DAT_O => s_DAT_O,
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DAT_O => s_DAT_O,
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ADR_O => s_ADR_O,
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ADR_O => s_ADR_O,
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CYC_O => s_CYC_O,
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CYC_O => s_CYC_O,
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STB_O => s_STB_O,
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STB_O => s_STB_O,
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ACK_I => s_ACK_I,
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ACK_I => s_ACK_I,
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WE_O => s_WE_O
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WE_O => s_WE_O
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);
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);
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U_EPPWBN_8TO16: eppwbn_width_extension
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U_EPPWBN_8TO16: eppwbn_width_extension
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generic map(
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generic map(
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TIME_OUT_VALUE => 255,
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TIME_OUT_VALUE => 1023,
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TIME_OUT_WIDTH => 8
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TIME_OUT_WIDTH => 10
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)
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)
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port map(
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port map(
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-- Master EPP to slave width exteneder
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-- Master EPP to slave width exteneder
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DAT_I_sl => s_DAT_O,
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DAT_I_sl => s_DAT_O,
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DAT_O_sl => s_DAT_I,
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DAT_O_sl => s_DAT_I,
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ADR_I_sl => s_ADR_O,
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ADR_I_sl => s_ADR_O,
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CYC_I_sl => s_CYC_O,
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CYC_I_sl => s_CYC_O,
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STB_I_sl => s_STB_O,
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STB_I_sl => s_STB_O,
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ACK_O_sl => s_ACK_I,
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ACK_O_sl => s_ACK_I,
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WE_I_sl => s_WE_O,
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WE_I_sl => s_WE_O,
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-- Master width exteneder to TOP
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-- Master width exteneder to TOP
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DAT_I_ma => DAT_I,
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DAT_I_ma => DAT_I,
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DAT_O_ma => DAT_O,
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DAT_O_ma => DAT_O,
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ADR_O_ma => ADR_O,
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ADR_O_ma => ADR_O,
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CYC_O_ma => CYC_O,
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CYC_O_ma => CYC_O,
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STB_O_ma => STB_O,
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STB_O_ma => STB_O,
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ACK_I_ma => ACK_I,
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ACK_I_ma => ACK_I,
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WE_O_ma => WE_O,
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WE_O_ma => WE_O,
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-- Common signals
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-- Common signals
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RST_I => RST_I,
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RST_I => RST_I,
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CLK_I => CLK_I
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CLK_I => CLK_I
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);
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);
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