-------------------------------------------------------------------------------------------------100
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| File: eppwbn_test.vhd
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--| File: eppwbn_test.vhd
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--| Version: 0.60
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--| Version: 0.60
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--| Tested in: Actel APA300, Actel A3PE1500
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--| Tested in: Actel APA300
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--| Tested in: Actel A3PE1500
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--| Board: RVI Prototype Board + LP Data Conversion Daughter Board
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This file is only for test purposes
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--| This file is only for test purposes
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--|
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--|
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.10 | jan-2008 | First release
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--| 0.10 | jan-2008 | First release
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--| 0.50 | jun-2009 | Sample testing signals
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--| 0.50 | jun-2009 | Testing signals
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--| 0.60 | jun-2009 | Sample testing instance for a dual port memory
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--| 0.60 | jun-2009 | Testing instance for the dual port memory
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.eppwbn_pkg.all;
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use work.eppwbn_pkg.all;
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entity eppwbn_16bit_test is
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entity eppwbn_16bit_test is
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generic(
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generic(
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-- Memoria hecha con registros puede causar módulos demasiado grandes.
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-- Memoria hecha con registros puede causar módulos demasiado grandes.
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-- Limitar el tamańo reduciéndo el tamańo del bus de direcciones
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-- Limitar el tamańo reduciéndo el tamańo del bus de direcciones
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ADD_WIDTH: integer := 4 -- máximo: 8
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ADD_WIDTH: integer := 4 -- máximo: 8
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);
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);
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port(
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port(
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-- al puerto EPP
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-- al puerto EPP
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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-- HostClk/nWrite
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-- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select)
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Sel: out std_logic; -- XFlag (Select)
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- a los switches
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-- a los switches
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rst: in std_logic; -- ATENCIÓN: entrada rst activo por bajo en instancia
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rst: in std_logic; -- ATENCIÓN: entrada rst activo por bajo en instancia
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-- al clock
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-- al clock
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clk: in std_logic;
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clk: in std_logic;
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-- monitores
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-- monitores
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display_cat: out std_logic;
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display_cat: out std_logic;
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data_monitor: out std_logic_vector (3 downto 0);
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data_monitor: out std_logic_vector (3 downto 0);
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select_nibble: in std_logic; -- Select data nibble. High: high nibble, low: ...
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select_nibble: in std_logic; -- Select data nibble. High: high nibble, low: ...
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epp_mode_monitor: out std_logic_vector (1 downto 0);
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epp_mode_monitor: out std_logic_vector (1 downto 0);
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nSelectIn_monitor:out std_logic;
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nSelectIn_monitor:out std_logic;
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nAutoFd_monitor: out std_logic;
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nAutoFd_monitor: out std_logic;
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nStrobe_monitor: out std_logic
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nStrobe_monitor: out std_logic
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);
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);
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end eppwbn_16bit_test;
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end eppwbn_16bit_test;
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architecture eppwbn_test_arch0 of eppwbn_16bit_test is
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architecture eppwbn_test_arch0 of eppwbn_16bit_test is
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signal DAT_I_master: std_logic_vector (15 downto 0);
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signal DAT_I_master: std_logic_vector (15 downto 0);
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signal DAT_O_master: std_logic_vector (15 downto 0);
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signal DAT_O_master: std_logic_vector (15 downto 0);
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signal ADR_O_master: std_logic_vector (7 downto 0);
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signal ADR_O_master: std_logic_vector (7 downto 0);
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signal CYC_O_master: std_logic;
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signal CYC_O_master: std_logic;
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signal STB_O_master: std_logic;
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signal STB_O_master: std_logic;
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signal ACK_I_master: std_logic;
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signal ACK_I_master: std_logic;
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signal WE_O_master: std_logic;
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signal WE_O_master: std_logic;
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signal clk_pll: std_logic;
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signal clk_pll: std_logic;
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signal gnd: std_logic;
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signal gnd: std_logic;
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signal s_not_rst: std_logic;
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signal s_not_rst: std_logic;
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signal s_not_epp_mode: std_logic_vector (1 downto 0);
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signal s_not_epp_mode: std_logic_vector (1 downto 0);
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signal s_to_mem_ADR_I_a: std_logic_vector(13 downto 0);
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signal s_to_mem_ADR_I_a: std_logic_vector(13 downto 0);
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begin
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begin
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gnd <= '0';
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gnd <= '0';
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s_not_rst <= not(rst);
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s_not_rst <= not(rst);
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data_monitor <= Data(7 downto 4) when select_nibble = '1' else
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data_monitor <= Data(7 downto 4) when select_nibble = '1' else
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Data(3 downto 0);
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Data(3 downto 0);
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display_cat <= '0';
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display_cat <= '0';
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epp_mode_monitor <= not(s_not_epp_mode);
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epp_mode_monitor <= not(s_not_epp_mode);
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nSelectIn_monitor <= nSelectIn;
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nSelectIn_monitor <= nSelectIn;
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nAutoFd_monitor <= nAutoFd;
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nAutoFd_monitor <= nAutoFd;
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nStrobe_monitor <= nStrobe;
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nStrobe_monitor <= nStrobe;
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-- SL_MEM1: eppwbn_16bit_test_wb_side
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-- SL_MEM1: eppwbn_16bit_test_wb_side
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-- generic map(
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-- generic map(
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-- ADD_WIDTH => ADD_WIDTH ,
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-- ADD_WIDTH => ADD_WIDTH ,
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-- WIDTH => 16
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-- WIDTH => 16
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-- )
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-- )
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-- port map(
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-- port map(
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-- RST_I => s_not_rst,
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-- RST_I => s_not_rst,
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-- CLK_I => clk_pll,
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-- CLK_I => clk_pll,
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-- DAT_I => DAT_O_master,
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-- DAT_I => DAT_O_master,
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-- DAT_O => DAT_I_master,
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-- DAT_O => DAT_I_master,
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-- ADR_I => ADR_O_master(ADD_WIDTH - 1 downto 0),
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-- ADR_I => ADR_O_master(ADD_WIDTH - 1 downto 0),
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-- CYC_I => CYC_O_master,
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-- CYC_I => CYC_O_master,
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-- STB_I => STB_O_master,
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-- STB_I => STB_O_master,
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-- ACK_O => ACK_I_master,
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-- ACK_O => ACK_I_master,
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-- WE_I => WE_O_master
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-- WE_I => WE_O_master
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-- );
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-- );
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s_to_mem_ADR_I_a <= (13 downto 8 => '0') & ADR_O_master;
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s_to_mem_ADR_I_a <= (13 downto 8 => '0') & ADR_O_master;
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SL_MEM2: dual_port_memory_wb port map(
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SL_MEM2: dual_port_memory_wb port map(
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-- Puerto A
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-- Puerto A
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RST_I_a => s_not_rst,
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RST_I_a => s_not_rst,
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CLK_I_a => clk_pll,
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CLK_I_a => clk_pll,
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DAT_I_a => DAT_O_master,
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DAT_I_a => DAT_O_master,
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DAT_O_a => DAT_I_master,
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DAT_O_a => DAT_I_master,
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ADR_I_a => s_to_mem_ADR_I_a,
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ADR_I_a => s_to_mem_ADR_I_a,
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CYC_I_a => CYC_O_master,
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CYC_I_a => CYC_O_master,
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STB_I_a => STB_O_master,
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STB_I_a => STB_O_master,
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ACK_O_a => ACK_I_master,
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ACK_O_a => ACK_I_master,
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WE_I_a => WE_O_master,
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WE_I_a => WE_O_master,
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-- Puerto B
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-- Puerto B
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RST_I_b => s_not_rst,
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RST_I_b => s_not_rst,
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CLK_I_b => '0',
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CLK_I_b => '0',
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DAT_I_b => (others => '0'),
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DAT_I_b => (others => '0'),
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ADR_I_b => (others => '0'),
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ADR_I_b => (others => '0'),
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CYC_I_b => '0',
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CYC_I_b => '0',
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STB_I_b => '0',
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STB_I_b => '0',
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WE_I_b => '0'
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WE_I_b => '0'
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);
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);
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MA_EPP: eppwbn_16bit port map(
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MA_EPP: eppwbn_16bit port map(
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-- Externo
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-- Externo
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nStrobe => nStrobe,
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nStrobe => nStrobe,
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Data => Data,
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Data => Data,
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nAck => nAck,
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nAck => nAck,
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busy => busy,
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busy => busy,
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PError => PError,
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PError => PError,
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Sel => Sel,
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Sel => Sel,
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nAutoFd => nAutoFd,
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nAutoFd => nAutoFd,
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PeriphLogicH => PeriphLogicH,
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PeriphLogicH => PeriphLogicH,
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nInit => nInit,
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nInit => nInit,
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nFault => nFault,
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nFault => nFault,
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nSelectIn => nSelectIn,
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nSelectIn => nSelectIn,
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-- Interno
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-- Interno
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RST_I => s_not_rst,
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RST_I => s_not_rst,
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CLK_I => clk_pll,
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CLK_I => clk_pll,
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DAT_I => DAT_I_master,
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DAT_I => DAT_I_master,
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DAT_O => DAT_O_master,
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DAT_O => DAT_O_master,
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ADR_O => ADR_O_master,
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ADR_O => ADR_O_master,
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CYC_O => CYC_O_master,
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CYC_O => CYC_O_master,
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STB_O => STB_O_master,
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STB_O => STB_O_master,
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ACK_I => ACK_I_master,
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ACK_I => ACK_I_master,
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WE_O => WE_O_master,
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WE_O => WE_O_master,
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-- MONITORES
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-- MONITORES
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-- TEMPORAL
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-- TEMPORAL
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epp_mode_monitor => s_not_epp_mode
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epp_mode_monitor => s_not_epp_mode
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);
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);
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PLL_0: component A3PE_pll
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PLL_0: component A3PE_pll
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port map(
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port map(
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POWERDOWN => '0',
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POWERDOWN => '0',
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CLKA => clk,
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CLKA => clk,
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LOCK => open,
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LOCK => open,
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--SDIN => '0',
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--SDIN => '0',
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--SCLK => '0',
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--SCLK => '0',
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--SSHIFT => '0',
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--SSHIFT => '0',
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--SUPDATE => '0',
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--SUPDATE => '0',
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--MODE => '0',
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--MODE => '0',
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GLA => clk_pll
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GLA => clk_pll
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--SDOUT => open
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--SDOUT => open
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);
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);
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