--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--|
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--|
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--| File: eppwbn_test_wb_side.vhd
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--| File: eppwbn_test_wb_side.vhd
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--| Version: 0.10
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--| Version: 0.10
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--| Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This file is only for test purposes
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--| This file is only for test purposes
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--| It only stores data in regiters with wishbone interconect
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--| It only stores data in regiters with wishbone interconect
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| File history:
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--| File history:
|
--| 0.10 | dic-2008 | First release
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--| 0.10 | dic-2008 | First release
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
|
--| This VHDL design file is an open design; you can redistribute it and/or
|
--| modify it and/or implement it after contacting the author.
|
--| modify it and/or implement it after contacting the author.
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|
|
|
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.eppwbn_pgk.all;
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use work.eppwbn_pkg.all;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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--use IEEE.STD_LOGIC_ARITH.ALL;
|
|
|
|
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entity eppwbn_16bit_test_wb_side is
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entity eppwbn_16bit_test_wb_side is
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|
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generic (
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generic (
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ADD_WIDTH : integer := 8;
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ADD_WIDTH : integer := 8;
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WIDTH : integer := 16
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WIDTH : integer := 16
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);
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);
|
|
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port(
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port(
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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DAT_I: in std_logic_vector (WIDTH-1 downto 0);
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DAT_I: in std_logic_vector (WIDTH-1 downto 0);
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DAT_O: out std_logic_vector (WIDTH-1 downto 0);
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DAT_O: out std_logic_vector (WIDTH-1 downto 0);
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ADR_I: in std_logic_vector (7 downto 0);
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ADR_I: in std_logic_vector (ADD_WIDTH-1 downto 0);
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CYC_I: in std_logic;
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CYC_I: in std_logic;
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STB_I: in std_logic;
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STB_I: in std_logic;
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ACK_O: out std_logic ;
|
ACK_O: out std_logic ;
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WE_I: in std_logic
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WE_I: in std_logic
|
);
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);
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end eppwbn_16bit_test_wb_side;
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end eppwbn_16bit_test_wb_side;
|
|
|
architecture eppwbn_test_wb_arch0 of eppwbn_16bit_test_wb_side is
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architecture eppwbn_test_wb_arch0 of eppwbn_16bit_test_wb_side is
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signal auto_ack: std_logic;
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signal auto_ack: std_logic;
|
begin
|
begin
|
|
|
MEM1: test_memory
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MEM1: test_memory
|
generic map(
|
generic map(
|
DEFAULT_OUT => '0',
|
DEFAULT_OUT => '0',
|
ADD_WIDTH => 8,
|
ADD_WIDTH => ADD_WIDTH,
|
WIDTH => WIDTH
|
WIDTH => WIDTH
|
)
|
)
|
port map (
|
port map (
|
cs => auto_ack,
|
cs => auto_ack,
|
clk => CLK_I,
|
clk => CLK_I,
|
reset => RST_I,
|
reset => RST_I,
|
add => ADR_I,
|
add => ADR_I,
|
Data_In => DAT_I,
|
Data_In => DAT_I,
|
Data_Out => DAT_O,
|
Data_Out => DAT_O,
|
WR => WE_I
|
WR => WE_I
|
);
|
);
|
auto_ack <= CYC_I and STB_I;
|
auto_ack <= CYC_I and STB_I;
|
ACK_O <= auto_ack;
|
ACK_O <= auto_ack;
|
|
|
|
|
|
|
|
|