--|------------------------------------------------------------------------------
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--|------------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--|
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--|
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--| File: eppwbn_wbn_side.vhd
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--| File: eppwbn_wbn_side.vhd
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--| Version: 0.10
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--| Version: 0.10
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--| Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This module controls the negotiation (IEEE Std. 1284-2000).
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--| This module controls the negotiation (IEEE Std. 1284-2000).
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--| This can be easily modified to control other modes besides the EPP.
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--| This can be easily modified to control other modes besides the EPP.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | nov-2008 | First testing release
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--| 0.01 | nov-2008 | First testing release
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--| 0.10 | dic-2008 | Customs signals without tri-state
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--| 0.10 | dic-2008 | Customs signals without tri-state
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| Copyright Facundo Aguilera 2008
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--| Copyright Facundo Aguilera 2008
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--| GPL
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--| GPL
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity eppwbn_ctrl is
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entity eppwbn_ctrl is
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port(
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port(
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-- salida al puerto epp
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-- salida al puerto epp
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000,
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284-2000,
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-- Negotiation/ECP/EPP (Compatibiliy)
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-- Negotiation/ECP/EPP (Compatibiliy)
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-- HostClk/nWrite
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-- HostClk/nWrite
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Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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Data: in std_logic_vector (7 downto 0); -- AD8..1/AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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-- Busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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-- Busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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Sel: out std_logic; -- XFlag (Select). Select no puede usarse
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- HostLogicH: in std_logic; -- (Host Logic High)
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-- HostLogicH: in std_logic; -- (Host Logic High)
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-- i indica misma señal de salida al puerto, aunque interna en el core y controlada por el bloque de control
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-- i indica misma señal de salida al puerto, aunque interna en el core y controlada por el bloque de control
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-- salida a la interface wishbone
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-- salida a la interface wishbone
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic;
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CLK_I: in std_logic;
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-- señales internas
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-- señales internas
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rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo
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rst_pp: out std_logic; -- generador de reset desde la interfaz del puerto paralelo
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epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp
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epp_mode: out std_logic_vector (1 downto 0) -- indicador de modo de comunicaci?n epp
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-- "00" deshabilitado
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-- "00" deshabilitado
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-- "01" inicial (se?ales de usuario e interrupciones deshabilitadas)
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-- "01" inicial (se?ales de usuario e interrupciones deshabilitadas)
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-- "10" sin definir
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-- "10" sin definir
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-- "11" modo EPP normal
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-- "11" modo EPP normal
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);
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);
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end entity eppwbn_ctrl;
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end entity eppwbn_ctrl;
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architecture
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architecture state_machines of eppwbn_ctrl is
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architecture state_machines of eppwbn_ctrl is
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type StateType is (
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type StateType is (
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st_compatibility_idle, -- Los estados corresponden a los especificados
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st_compatibility_idle, -- Los estados corresponden a los especificados
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st_negotiation2, -- por el est?ndar.
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st_negotiation2, -- por el est?ndar.
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-- Los n?meros de los estados negotiation corresponden
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-- Los n?meros de los estados negotiation corresponden
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-- a las fases del est?ndar.
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-- a las fases del est?ndar.
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st_initial_epp,
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st_initial_epp,
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st_epp_mode
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st_epp_mode
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-- otros modos
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-- otros modos
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);
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);
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signal next_state, present_state: StateType;
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signal next_state, present_state: StateType;
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signal ext_req_val: std_logic_vector (7 downto 0);
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signal ext_req_val: std_logic_vector (7 downto 0);
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begin
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begin
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- generación de señal de reset para otros módulos y señal de encendido hacia el host
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-- generación de señal de reset para otros módulos y señal de encendido hacia el host
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rst_pp <= not(nInit) and not(nSelectIn); -- (nInit = '0') and (nSelectIn = '0');
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rst_pp <= not(nInit) and not(nSelectIn); -- (nInit = '0') and (nSelectIn = '0');
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PeriphLogicH <= '1';
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PeriphLogicH <= '1';
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- almacenamiento de Extensibility Request Value (asíncrono)
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-- almacenamiento de Extensibility Request Value (asíncrono)
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P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn)
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P_data_store: process(nStrobe, present_state, Data, RST_I, nInit, nSelectIn)
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begin
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begin
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if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
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if (RST_I = '1' or (nInit = '0' and nSelectIn = '0')) then
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ext_req_val <= (others => '0');
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ext_req_val <= (others => '0');
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elsif (present_state = st_negotiation2 and nStrobe'event and nStrobe = '0') then
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elsif (present_state = st_negotiation2 and nStrobe'event and nStrobe = '0') then
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ext_req_val <= Data;
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ext_req_val <= Data;
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end if;
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end if;
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end process P_data_store;
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end process P_data_store;
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- selección de estado siguiente
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-- selección de estado siguiente
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P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin
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P_state_comb: process(present_state, next_state, RST_I, nSelectIn, nAutoFd, ext_req_val, nInit, nStrobe) begin
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if RST_I = '1' then
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if RST_I = '1' then
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PError <= '-';
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PError <= '-';
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nFault <= '-';
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nFault <= '-';
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Sel <= '-';
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Sel <= '-';
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nAck <= '-';
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nAck <= '-';
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epp_mode <= "--";
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epp_mode <= "--";
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next_state <= st_compatibility_idle;
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next_state <= st_compatibility_idle;
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else
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else
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case present_state is
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case present_state is
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when st_compatibility_idle =>
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when st_compatibility_idle =>
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PError <= '0';
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PError <= '0';
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nFault <= '1';
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nFault <= '1';
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Sel <= '1';
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Sel <= '1';
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nAck <= '1';
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nAck <= '1';
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epp_mode <= "00";
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epp_mode <= "00";
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-- verificación de compatibilidad con 1284
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-- verificación de compatibilidad con 1284
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if (nAutoFd = '0' and nSelectIn = '1') then
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if (nAutoFd = '0' and nSelectIn = '1') then
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next_state <= st_negotiation2;
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next_state <= st_negotiation2;
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else
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else
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next_state <= st_compatibility_idle;
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next_state <= st_compatibility_idle;
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end if;
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end if;
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when st_negotiation2 =>
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when st_negotiation2 =>
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PError <= '1';
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PError <= '1';
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nFault <= '1';
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nFault <= '1';
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Sel <= '1';
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Sel <= '1';
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nAck <= '0';
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nAck <= '0';
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epp_mode <= "00";
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epp_mode <= "00";
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-- Reconocimiento del host
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-- Reconocimiento del host
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if (nStrobe = '1' and
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if (nStrobe = '1' and
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nAutoFd = '1') then
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nAutoFd = '1') then
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-- Pedido de modo EPP
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-- Pedido de modo EPP
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if (ext_req_val = "01000000") then
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if (ext_req_val = "01000000") then
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next_state <= st_initial_epp;
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next_state <= st_initial_epp;
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-- Otros modos
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-- Otros modos
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else
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else
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next_state <= st_compatibility_idle;
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next_state <= st_compatibility_idle;
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end if;
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end if;
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else
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else
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next_state <= st_negotiation2;
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next_state <= st_negotiation2;
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end if;
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end if;
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when st_initial_epp =>
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when st_initial_epp =>
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Sel <= '1';
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Sel <= '1';
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PError <= '1';
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PError <= '1';
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nFault <= '1';
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nFault <= '1';
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nAck <= '1';
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nAck <= '1';
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epp_mode <= "01";
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epp_mode <= "01";
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-- Finalizaci?n del modo EPP
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-- Finalizaci?n del modo EPP
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if nInit = '0' then
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if nInit = '0' then
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next_state <= st_compatibility_idle;
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next_state <= st_compatibility_idle;
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-- Comienzo del primer ciclo EPP
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-- Comienzo del primer ciclo EPP
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elsif (nSelectIn = '0' or nAutoFd = '0') then
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elsif (nSelectIn = '0' or nAutoFd = '0') then
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next_state <= st_epp_mode;
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next_state <= st_epp_mode;
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else
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else
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next_state <= st_initial_epp;
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next_state <= st_initial_epp;
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end if;
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end if;
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when st_epp_mode =>
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when st_epp_mode =>
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Sel <= '0'; -- El bus debe asegurar que se puedan usar
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Sel <= '0'; -- El bus debe asegurar que se puedan usar
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PError <= '0'; -- las señales definidas por el usuario en el módulo
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PError <= '0'; -- las señales definidas por el usuario en el módulo
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nFault <= '0'; -- EPP.
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nFault <= '0'; -- EPP.
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nAck <= '0';
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nAck <= '0';
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epp_mode <= "11";
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epp_mode <= "11";
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-- Finalizaci?n del modo EPP
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-- Finalizaci?n del modo EPP
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next_state <= st_epp_mode;
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next_state <= st_epp_mode;
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-- Se sale de este estado en forma asíncrona ya que esta acción
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-- Se sale de este estado en forma asíncrona ya que esta acción
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end case; -- no tiene handshake.
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end case; -- no tiene handshake.
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end if;
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end if;
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end process P_state_comb;
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end process P_state_comb;
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----------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------
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-- establecimiento de estado actual
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-- establecimiento de estado actual
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P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
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P_state_clocked: process(CLK_I, nInit, nSelectIn) begin
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if (nInit = '0' and nSelectIn = '0') then
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if (nInit = '0' and nSelectIn = '0') then
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present_state <= st_compatibility_idle;
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present_state <= st_compatibility_idle;
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elsif present_state = st_epp_mode and nInit = '0' then
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elsif present_state = st_epp_mode and nInit = '0' then
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present_state <= st_compatibility_idle;
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present_state <= st_compatibility_idle;
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elsif (CLK_I'event and CLK_I='1') then
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elsif (CLK_I'event and CLK_I='1') then
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present_state <= next_state;
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present_state <= next_state;
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end if;
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end if;
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end process P_state_clocked;
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end process P_state_clocked;
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