--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| UNSL - Modular Oscilloscope
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--| UNSL - Modular Oscilloscope
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--|
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--|
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--| File: eppwbn_test.vhd
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--| File: eppwbn_test.vhd
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--| Version: 0.10
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--| Version: 0.10
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--| Targeted device: Actel A3PE1500
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--| Targeted device: Actel A3PE1500
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--|-----------------------------------------------------------------------------
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--|-----------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| This file is only for test purposes
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--| This file is only for test purposes
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--|
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--|
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.10 | jan-2008 | First release
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--| 0.10 | jan-2008 | First release
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.eppwbn_pgk.all;
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use work.eppwbn_pkg.all;
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entity eppwbn_test is
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entity eppwbn_test is
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port(
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port(
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-- al puerto EPP
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-- al puerto EPP
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284
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-- HostClk/nWrite
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-- HostClk/nWrite
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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nAck: out std_logic; -- PtrClk/PeriphClk/Intr
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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busy: out std_logic; -- PtrBusy/PeriphAck/nWait
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PError: out std_logic; -- AckData/nAckReverse
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PError: out std_logic; -- AckData/nAckReverse
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Sel: out std_logic; -- XFlag (Select)
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Sel: out std_logic; -- XFlag (Select)
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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PeriphLogicH: out std_logic; -- (Periph Logic High)
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nInit: in std_logic; -- nReverseRequest
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nInit: in std_logic; -- nReverseRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nFault: out std_logic; -- nDataAvail/nPeriphRequest
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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nSelectIn: in std_logic; -- 1284 Active/nAStrb
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-- a los switches
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-- a los switches
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rst: in std_logic;
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rst: in std_logic;
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-- al clock
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-- al clock
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clk: in std_logic
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clk: in std_logic
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-- a los leds
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-- a los leds
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--epp_mode: out std_logic_vector(1 downto 0);
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--epp_mode: out std_logic_vector(1 downto 0);
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--nAck_monitor: out std_logic;
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--nAck_monitor: out std_logic;
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--busy_monitor: out std_logic;
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--busy_monitor: out std_logic;
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--PError_monitor: out std_logic;
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--PError_monitor: out std_logic;
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--Sel_monitor: out std_logic;
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--Sel_monitor: out std_logic;
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--nFault_monitor: out std_logic;
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--nFault_monitor: out std_logic;
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-- nAutoFd_monitor: out std_logic;
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-- nAutoFd_monitor: out std_logic;
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-- nInit_monitor: out std_logic;
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-- nInit_monitor: out std_logic;
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-- nSelectIn_monitor: out std_logic;
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-- nSelectIn_monitor: out std_logic;
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-- nStrobe_monitor: out std_logic
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-- nStrobe_monitor: out std_logic
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--PeriphLogicH_monitor: out std_logic;
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--PeriphLogicH_monitor: out std_logic;
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);
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);
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end eppwbn_test;
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end eppwbn_test;
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architecture eppwbn_test_arch0 of eppwbn_test is
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architecture eppwbn_test_arch0 of eppwbn_test is
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signal DAT_I_master: std_logic_vector (7 downto 0);
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signal DAT_I_master: std_logic_vector (7 downto 0);
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signal DAT_O_master: std_logic_vector (7 downto 0);
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signal DAT_O_master: std_logic_vector (7 downto 0);
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signal ADR_O_master: std_logic_vector (7 downto 0);
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signal ADR_O_master: std_logic_vector (7 downto 0);
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signal CYC_O_master: std_logic;
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signal CYC_O_master: std_logic;
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signal STB_O_master: std_logic;
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signal STB_O_master: std_logic;
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signal ACK_I_master: std_logic;
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signal ACK_I_master: std_logic;
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signal WE_O_master: std_logic;
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signal WE_O_master: std_logic;
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signal clk_pll: std_logic;
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signal clk_pll: std_logic;
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begin
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begin
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SL_MEM1: eppwbn_test_wb_side
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SL_MEM1: eppwbn_test_wb_side
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port map(
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port map(
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RST_I => rst,
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RST_I => rst,
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CLK_I => clk_pll,
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CLK_I => clk_pll,
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DAT_I => DAT_O_master,
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DAT_I => DAT_O_master,
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DAT_O => DAT_I_master,
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DAT_O => DAT_I_master,
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ADR_I => ADR_O_master,
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ADR_I => ADR_O_master,
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CYC_I => CYC_O_master,
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CYC_I => CYC_O_master,
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STB_I => STB_O_master,
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STB_I => STB_O_master,
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ACK_O => ACK_I_master,
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ACK_O => ACK_I_master,
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WE_I => WE_O_master
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WE_I => WE_O_master
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);
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);
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MA_EPP: eppwbn port map(
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MA_EPP: eppwbn port map(
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-- Externo
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-- Externo
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nStrobe => nStrobe,
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nStrobe => nStrobe,
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Data => Data,
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Data => Data,
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nAck => nAck,
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nAck => nAck,
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busy => busy,
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busy => busy,
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PError => PError,
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PError => PError,
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Sel => Sel,
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Sel => Sel,
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nAutoFd => nAutoFd,
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nAutoFd => nAutoFd,
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PeriphLogicH => PeriphLogicH,
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PeriphLogicH => PeriphLogicH,
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nInit => nInit,
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nInit => nInit,
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nFault => nFault,
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nFault => nFault,
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nSelectIn => nSelectIn,
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nSelectIn => nSelectIn,
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-- Interno
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-- Interno
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RST_I => rst,
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RST_I => rst,
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CLK_I => clk_pll,
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CLK_I => clk_pll,
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DAT_I => DAT_I_master,
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DAT_I => DAT_I_master,
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DAT_O => DAT_O_master,
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DAT_O => DAT_O_master,
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ADR_O => ADR_O_master,
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ADR_O => ADR_O_master,
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CYC_O => CYC_O_master,
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CYC_O => CYC_O_master,
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STB_O => STB_O_master,
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STB_O => STB_O_master,
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ACK_I => ACK_I_master,
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ACK_I => ACK_I_master,
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WE_O => WE_O_master
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WE_O => WE_O_master
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);
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);
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PLL_0: pll port map(
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PLL_0: pll port map(
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GLB => clk_pll,
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GLB => clk_pll,
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CLK => clk
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CLK => clk
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);
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);
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