----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Modular Oscilloscope
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--| UNSL - Argentine
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--|
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--|
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--| Version: 0.01
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--| Version: 0.01
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--| Tested in: Actel APA300
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--| Tested in: Actel APA300
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Description:
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--| EPP - Wishbone bridge.
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--| EPP - Wishbone bridge.
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--| Convert 8 to 16 bits width data bus
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--| Convert 8 to 16 bits width data bus
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--|-------------------------------------------------------------------------------------------------
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| File history:
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--| 0.01 | mar-2009 | First release
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--| 0.01 | mar-2009 | First release
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--| Copyright ® 2008, Facundo Aguilera.
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--| Copyright ® 2008, Facundo Aguilera.
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--|
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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--| modify it and/or implement it after contacting the author.
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--| Wishbone Rev. B.3 compatible
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--| Wishbone Rev. B.3 compatible
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----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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-- COMO USAR:
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-- COMO USAR:
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-- Puente entre un bus de datos de 8 bit (esclavo) y otro de 16 bit (maestro). cada dos acciones del
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-- Puente entre un bus de datos de 8 bit (esclavo) y otro de 16 bit (maestro). cada dos acciones del
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-- lado de 8 bit realiza una en en lado de 16. Posee un timer configurable con el que vuelve al
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-- lado de 8 bit realiza una en en lado de 16. Posee un timer configurable con el que vuelve al
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-- estado inicial luego de sierto tiempo (ningun byte leido). También vuelve al estado inicial al
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-- estado inicial luego de sierto tiempo (ningun byte leido). También vuelve al estado inicial al
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-- hacer un cambio de dirección, por lo que puede realizarse una sincronización inicial haciendo un
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-- hacer un cambio de dirección, por lo que puede realizarse una sincronización inicial haciendo un
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-- cambio de dirección de escritura.
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-- cambio de dirección de escritura.
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.eppwbn_pgk.all;
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use work.eppwbn_pkg.all;
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entity eppwbn_width_extension is
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entity eppwbn_width_extension is
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generic (
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generic (
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TIME_OUT_VALUE: integer := 255;
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TIME_OUT_VALUE: integer := 255;
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TIME_OUT_WIDTH: integer := 8
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TIME_OUT_WIDTH: integer := 8
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);
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);
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port(
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port(
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-- Slave signals
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-- Slave signals
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DAT_I_sl: in std_logic_vector (7 downto 0);
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DAT_I_sl: in std_logic_vector (7 downto 0);
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DAT_O_sl: out std_logic_vector (7 downto 0);
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DAT_O_sl: out std_logic_vector (7 downto 0);
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ADR_I_sl: in std_logic_vector (7 downto 0);
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ADR_I_sl: in std_logic_vector (7 downto 0);
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CYC_I_sl: in std_logic;
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CYC_I_sl: in std_logic;
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STB_I_sl: in std_logic;
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STB_I_sl: in std_logic;
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ACK_O_sl: out std_logic ;
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ACK_O_sl: out std_logic ;
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WE_I_sl: in std_logic;
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WE_I_sl: in std_logic;
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-- Master signals
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-- Master signals
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DAT_I_ma: in std_logic_vector (15 downto 0);
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DAT_I_ma: in std_logic_vector (15 downto 0);
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DAT_O_ma: out std_logic_vector (15 downto 0);
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DAT_O_ma: out std_logic_vector (15 downto 0);
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ADR_O_ma: out std_logic_vector (7 downto 0);
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ADR_O_ma: out std_logic_vector (7 downto 0);
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CYC_O_ma: out std_logic;
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CYC_O_ma: out std_logic;
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STB_O_ma: out std_logic;
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STB_O_ma: out std_logic;
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ACK_I_ma: in std_logic ;
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ACK_I_ma: in std_logic ;
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WE_O_ma: out std_logic;
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WE_O_ma: out std_logic;
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-- Common signals
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-- Common signals
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RST_I: in std_logic;
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RST_I: in std_logic;
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CLK_I: in std_logic
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CLK_I: in std_logic
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);
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);
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end entity eppwbn_width_extension;
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end entity eppwbn_width_extension;
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architecture arch_0 of eppwbn_width_extension is
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architecture arch_0 of eppwbn_width_extension is
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type StateType is (
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type StateType is (
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st_low,
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st_low,
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st_high
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st_high
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);
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);
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signal next_state, present_state: StateType;
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signal next_state, present_state: StateType;
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signal dat_reg, adr_reg: std_logic_vector (7 downto 0); -- Almacena temporalmente las entradas
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signal dat_reg, adr_reg: std_logic_vector (7 downto 0); -- Almacena temporalmente las entradas
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signal timer, time_out_ref: std_logic_vector (TIME_OUT_WIDTH - 1 downto 0);
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signal timer, time_out_ref: std_logic_vector (TIME_OUT_WIDTH - 1 downto 0);
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begin
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begin
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ADR_O_ma <= ADR_I_sl;
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ADR_O_ma <= ADR_I_sl;
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time_out_ref <= conv_std_logic_vector(TIME_OUT_VALUE, TIME_OUT_WIDTH);
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time_out_ref <= conv_std_logic_vector(TIME_OUT_VALUE, TIME_OUT_WIDTH);
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P_state_comb: process(DAT_I_sl,CYC_I_sl,STB_I_sl,WE_I_sl,ACK_I_ma,present_state,ADR_I_sl,
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P_state_comb: process(DAT_I_sl,CYC_I_sl,STB_I_sl,WE_I_sl,ACK_I_ma,present_state,ADR_I_sl,
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DAT_I_ma,dat_reg,adr_reg,timer,time_out_ref)
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DAT_I_ma,dat_reg,adr_reg,timer,time_out_ref)
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begin
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begin
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case present_state is
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case present_state is
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-- Escritura: Señales de hadshake provistas por el módulo. Se guarda byte bajo.
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-- Escritura: Señales de hadshake provistas por el módulo. Se guarda byte bajo.
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-- Lectura: Señales de hadshake provistas por fuente. Se guarda byte alto.
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-- Lectura: Señales de hadshake provistas por fuente. Se guarda byte alto.
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when st_low =>
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when st_low =>
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WE_O_ma <= '0';
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WE_O_ma <= '0';
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DAT_O_ma <= (others => '0');
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DAT_O_ma <= (others => '0');
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DAT_O_sl <= DAT_I_ma(7 downto 0);
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DAT_O_sl <= DAT_I_ma(7 downto 0);
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if WE_I_sl = '1' then
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if WE_I_sl = '1' then
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CYC_O_ma <= '0'; -- Esperar hasta recibir el proximo byte
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CYC_O_ma <= '0'; -- Esperar hasta recibir el proximo byte
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STB_O_ma <= '0';
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STB_O_ma <= '0';
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ACK_O_sl <= CYC_I_sl and STB_I_sl; -- Genera autorespuesta
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ACK_O_sl <= CYC_I_sl and STB_I_sl; -- Genera autorespuesta
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else
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else
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CYC_O_ma <= CYC_I_sl;
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CYC_O_ma <= CYC_I_sl;
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STB_O_ma <= STB_I_sl;
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STB_O_ma <= STB_I_sl;
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ACK_O_sl <= ACK_I_ma;
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ACK_O_sl <= ACK_I_ma;
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end if;
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end if;
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if (CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl = '1' or ACK_I_ma = '1') then
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if (CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl = '1' or ACK_I_ma = '1') then
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next_state <= st_high;
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next_state <= st_high;
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else
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else
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next_state <= st_low;
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next_state <= st_low;
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end if;
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end if;
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-- Escritura: Señales de hadshake provistas por fuentepor el módulo.
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-- Escritura: Señales de hadshake provistas por fuentepor el módulo.
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-- Lectura: Señales de hadshake provistas por el módulo.
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-- Lectura: Señales de hadshake provistas por el módulo.
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when others =>
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when others =>
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WE_O_ma <= WE_I_sl;
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WE_O_ma <= WE_I_sl;
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DAT_O_ma <= DAT_I_sl & dat_reg;
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DAT_O_ma <= DAT_I_sl & dat_reg;
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DAT_O_sl <= dat_reg;
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DAT_O_sl <= dat_reg;
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if adr_reg = ADR_I_sl then
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if adr_reg = ADR_I_sl then
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if WE_I_sl = '1' then
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if WE_I_sl = '1' then
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CYC_O_ma <= CYC_I_sl; -- Usa señales de la fuente
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CYC_O_ma <= CYC_I_sl; -- Usa señales de la fuente
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STB_O_ma <= STB_I_sl;
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STB_O_ma <= STB_I_sl;
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ACK_O_sl <= ACK_I_ma;
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ACK_O_sl <= ACK_I_ma;
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else
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else
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CYC_O_ma <= '0';
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CYC_O_ma <= '0';
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STB_O_ma <= '0';
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STB_O_ma <= '0';
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ACK_O_sl <= CYC_I_sl and STB_I_sl; -- Genera autorespuesta
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ACK_O_sl <= CYC_I_sl and STB_I_sl; -- Genera autorespuesta
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end if;
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end if;
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else
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else
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CYC_O_ma <= '0';
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CYC_O_ma <= '0';
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STB_O_ma <= '0';
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STB_O_ma <= '0';
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ACK_O_sl <= '0';
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ACK_O_sl <= '0';
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end if;
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end if;
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if ((CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl /= '1' or ACK_I_ma = '1'))
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if ((CYC_I_sl = '1' and STB_I_sl = '1') and (WE_I_sl /= '1' or ACK_I_ma = '1'))
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or ((CYC_I_sl = '1' and STB_I_sl = '1') and (ADR_I_sl /= adr_reg))
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or ((CYC_I_sl = '1' and STB_I_sl = '1') and (ADR_I_sl /= adr_reg))
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or (timer >= time_out_ref) then
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or (timer >= time_out_ref) then
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next_state <= st_low;
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next_state <= st_low;
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else
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else
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next_state <= st_high;
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next_state <= st_high;
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end if;
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end if;
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end case;
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end case;
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end process;
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end process;
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P_state_clocked: process(RST_I,CLK_I,next_state,timer)
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P_state_clocked: process(RST_I,CLK_I,next_state,timer)
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begin
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begin
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if RST_I = '1' then
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if RST_I = '1' then
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present_state <= st_low;
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present_state <= st_low;
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timer <= (others => '0');
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timer <= (others => '0');
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dat_reg <= (others => '0');
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dat_reg <= (others => '0');
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adr_reg <= (others => '0');
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adr_reg <= (others => '0');
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elsif CLK_I'event and CLK_I = '1' then
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elsif CLK_I'event and CLK_I = '1' then
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-- Resgistrar los valores si va a cambir al estado st_high
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-- Resgistrar los valores si va a cambir al estado st_high
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if next_state = st_high and present_state = st_low then
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if next_state = st_high and present_state = st_low then
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adr_reg <= ADR_I_sl;
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adr_reg <= ADR_I_sl;
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if WE_I_sl = '1' then
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if WE_I_sl = '1' then
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dat_reg <= DAT_I_sl; -- Guarda byte bajo
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dat_reg <= DAT_I_sl; -- Guarda byte bajo
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else
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else
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dat_reg <= DAT_I_ma(15 downto 8);
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dat_reg <= DAT_I_ma(15 downto 8);
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end if;
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end if;
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end if;
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end if;
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-- Configuración del timer
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-- Configuración del timer
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if present_state = st_high then
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if present_state = st_high then
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timer <= timer + 1;
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timer <= timer + 1;
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else
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else
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timer <= (others => '0');
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timer <= (others => '0');
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end if;
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end if;
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-- Cambio de estado
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-- Cambio de estado
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present_state <= next_state;
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present_state <= next_state;
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end if;
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end if;
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end process;
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end process;
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end architecture arch_0;
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end architecture arch_0;
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