// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2022-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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package mpmc10_pkg;
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package mpmc10_pkg;
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parameter CACHE_ASSOC = 4;
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parameter CACHE_ASSOC = 4;
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parameter RMW = 0;
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parameter RMW = 0;
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parameter NAR = 2;
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parameter NAR = 2;
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parameter AMSB = 28;
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parameter AMSB = 28;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter CMD_READ = 3'b001;
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parameter CMD_READ = 3'b001;
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parameter CMD_WRITE = 3'b000;
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parameter CMD_WRITE = 3'b000;
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// State machine states
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// State machine states
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typedef enum logic [3:0] {
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typedef enum logic [4:0] {
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IDLE = 4'd0,
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IDLE = 5'd0,
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PRESET1 = 4'd1,
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PRESET1 = 5'd1,
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PRESET2 = 4'd2,
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PRESET2 = 5'd2,
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WRITE_DATA0 = 4'd3,
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WRITE_DATA0 = 5'd3,
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WRITE_DATA1 = 4'd4,
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WRITE_DATA1 = 5'd4,
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WRITE_DATA2 = 4'd5,
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WRITE_DATA2 = 5'd5,
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WRITE_DATA3 = 4'd6,
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WRITE_DATA3 = 5'd6,
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READ_DATA = 4'd7,
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READ_DATA = 5'd7,
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READ_DATA0 = 4'd8,
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READ_DATA0 = 5'd8,
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READ_DATA1 = 4'd9,
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READ_DATA1 = 5'd9,
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READ_DATA2 = 4'd10,
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READ_DATA2 = 5'd10,
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WAIT_NACK = 4'd11,
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WAIT_NACK = 5'd11,
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WRITE_TRAMP = 4'd12, // write trampoline
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WRITE_TRAMP = 5'd12, // write trampoline
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WRITE_TRAMP1 = 4'd13,
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WRITE_TRAMP1 = 5'd13,
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PRESET3 = 4'd14
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PRESET3 = 5'd14,
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ALU = 5'd15,
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ALU1 = 5'd16,
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ALU2 = 5'd17,
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ALU3 = 5'd18,
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ALU4 = 5'd19,
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CAS = 5'd20
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} mpmc10_state_t;
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} mpmc10_state_t;
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typedef struct packed
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typedef struct packed
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{
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{
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logic [31:4] tag;
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logic [31:4] tag;
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logic modified;
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logic modified;
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logic [127:0] data;
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logic [127:0] data;
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} mpmc10_cache_line_t;
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} mpmc10_cache_line_t;
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typedef struct packed
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typedef struct packed
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{
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{
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mpmc10_cache_line_t [CACHE_ASSOC-1:0] lines;
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mpmc10_cache_line_t [CACHE_ASSOC-1:0] lines;
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} mpmc10_quad_cache_line_t;
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} mpmc10_quad_cache_line_t;
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endpackage
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endpackage
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