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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_state_machine_wb.sv] - Diff between revs 7 and 11

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Rev 7 Rev 11
`timescale 1ns / 1ps
`timescale 1ns / 1ps
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
//   \\__/ o\    (C) 2015-2023  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
// BSD 3-Clause License
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// modification, are permitted provided that the following conditions are met:
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// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
//    list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
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// 3. Neither the name of the copyright holder nor the names of its
//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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// ============================================================================
// ============================================================================
//
//
import mpmc10_pkg::*;
import mpmc10_pkg::*;
module mpmc10_state_machine_wb(rst, clk, calib_complete, to, rdy, wdf_rdy, fifo_empty,
module mpmc10_state_machine_wb(rst, clk, calib_complete, to, rdy, wdf_rdy, fifo_empty,
        rd_rst_busy, fifo_out, state,
        rd_rst_busy, fifo_out, state,
        num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid);
        num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid, rmw_hit);
input rst;
input rst;
input clk;
input clk;
input calib_complete;
input calib_complete;
input to;                                                       // state machine time-out
input to;                                                       // state machine time-out
input rdy;
input rdy;
input wdf_rdy;
input wdf_rdy;
input fifo_empty;
input fifo_empty;
input rd_rst_busy;
input rd_rst_busy;
input wb_write_request128_t fifo_out;
input wb_cmd_request128_t fifo_out;
output mpmc10_state_t state;
output mpmc10_state_t state;
input [5:0] num_strips;
input [5:0] num_strips;
input [5:0] req_strip_cnt;
input [5:0] req_strip_cnt;
input [5:0] resp_strip_cnt;
input [5:0] resp_strip_cnt;
input rd_data_valid;
input rd_data_valid;
 
input rmw_hit;
 
 
mpmc10_state_t next_state;
mpmc10_state_t next_state;
always_ff @(posedge clk)
always_ff @(posedge clk)
        state <= next_state;
        state <= next_state;
always_comb
always_comb
if (rst)
if (rst)
        next_state <= IDLE;
        next_state <= IDLE;
else begin
else begin
        case(state)
        case(state)
        IDLE:
        IDLE:
                if (!fifo_empty && !rd_rst_busy && calib_complete)
                if (!fifo_empty && !rd_rst_busy && calib_complete)
                        next_state <= PRESET1;
                        next_state <= PRESET1;
                else
                else
                        next_state <= IDLE;
                        next_state <= IDLE;
        PRESET1:
        PRESET1:
                next_state <= PRESET2;
                next_state <= PRESET2;
        PRESET2:
        PRESET2:
                next_state <= PRESET3;
                next_state <= PRESET3;
        PRESET3:
        PRESET3:
                if (fifo_out.stb & fifo_out.we)
                if (fifo_out.stb && fifo_out.cmd==CMD_STORE)
                        next_state <= WRITE_DATA0;
                        next_state <= WRITE_DATA0;
                else
                else
                        next_state <= READ_DATA0;
                        next_state <= READ_DATA0;
        // Write data to the data fifo
        // Write command to the command fifo
        // Write occurs when app_wdf_wren is true and app_wdf_rdy is true
        // Write occurs when app_rdy is true
        WRITE_DATA0:
        WRITE_DATA0:
                // Issue a write command if the fifo is full.
                if (rdy)// && req_strip_cnt==num_strips)
        //      if (!app_wdf_rdy)
 
        //              next_state <= WRITE_DATA1;
 
        //      else
 
                if (wdf_rdy)// && req_strip_cnt==num_strips)
 
                        next_state <= WRITE_DATA1;
                        next_state <= WRITE_DATA1;
                else
                else
                        next_state <= WRITE_DATA0;
                        next_state <= WRITE_DATA0;
        WRITE_DATA1:
        WRITE_DATA1:
                next_state <= WRITE_DATA2;
                next_state <= WRITE_DATA2;
        WRITE_DATA2:
        WRITE_DATA2:
                if (rdy)
                if (rdy)
                        next_state <= WRITE_DATA3;
                        next_state <= WRITE_DATA3;
                else
                else
                        next_state <= WRITE_DATA2;
                        next_state <= WRITE_DATA2;
 
        // Write data to the data fifo
 
        // Write occurs when app_wdf_wren is true and app_wdf_rdy is true
        WRITE_DATA3:
        WRITE_DATA3:
 
                if (wdf_rdy)
                next_state <= IDLE;
                next_state <= IDLE;
 
                else
 
                        next_state <= WRITE_DATA3;
 
 
        // There could be multiple read requests submitted before any response occurs.
        // There could be multiple read requests submitted before any response occurs.
        // Stay in the SET_CMD_RD until all requested strips have been processed.
        // Stay in the SET_CMD_RD until all requested strips have been processed.
        READ_DATA0:
        READ_DATA0:
                next_state <= READ_DATA1;
                next_state <= READ_DATA1;
        // Could it take so long to do the request that we start getting responses
        // Could it take so long to do the request that we start getting responses
        // back?
        // back?
        READ_DATA1:
        READ_DATA1:
                if (rdy && req_strip_cnt==num_strips)
                if (rdy && req_strip_cnt==num_strips)
                        next_state <= READ_DATA2;
                        next_state <= READ_DATA2;
                else
                else
                        next_state <= READ_DATA1;
                        next_state <= READ_DATA1;
        // Wait for incoming responses, but only for so long to prevent a hang.
        // Wait for incoming responses, but only for so long to prevent a hang.
        READ_DATA2:
        READ_DATA2:
                if (rd_data_valid && resp_strip_cnt==num_strips)
                if (rd_data_valid && resp_strip_cnt==num_strips) begin
 
                        case(fifo_out.cmd)
 
                        CMD_LOAD,CMD_LOADZ:
 
                                next_state <= WAIT_NACK;
 
                        CMD_ADD,CMD_OR,CMD_AND,CMD_EOR,CMD_ASL,CMD_LSR,
 
                        CMD_MIN,CMD_MAX,CMD_MINU,CMD_MAXU,CMD_CAS:
 
                                next_state <= ALU;
 
                        default:
                        next_state <= WAIT_NACK;
                        next_state <= WAIT_NACK;
 
                        endcase
 
                end
                else
                else
                        next_state <= READ_DATA2;
                        next_state <= READ_DATA2;
 
 
 
        ALU:
 
                if (rmw_hit)
 
                        next_state <= ALU1;
 
        ALU1:
 
                next_state <= ALU2;
 
        ALU2:
 
                next_state <= ALU3;
 
        ALU3:
 
                next_state <= ALU4;
 
        ALU4:
 
                next_state <= WRITE_TRAMP1;
 
 
 
        WRITE_TRAMP1:
 
                next_state <= WRITE_DATA0;
 
 
        WAIT_NACK:
        WAIT_NACK:
                // If we're not seeing a nack and there is a channel selected, then the
                // If we're not seeing a nack and there is a channel selected, then the
                // cache tag must not have updated correctly.
                // cache tag must not have updated correctly.
                // For writes, assume a nack by now.
                // For writes, assume a nack by now.
                next_state <= IDLE;
                next_state <= IDLE;
        default:        next_state <= IDLE;
        default:        next_state <= IDLE;
        endcase
        endcase
        // Is the state machine hung? Do not time out during calibration.
        // Is the state machine hung? Do not time out during calibration.
        if (to && calib_complete)
        if (to && calib_complete)
                next_state <= IDLE;
                next_state <= IDLE;
end
end
endmodule
endmodule
 
 

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