from myhdl import *
|
from myhdl import *
|
|
|
ACTIVE_LOW = bool(0)
|
ACTIVE_LOW = bool(0)
|
FRAME_SIZE = 8
|
FRAME_SIZE = 8
|
t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
|
t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
|
|
|
def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
|
def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
|
|
|
""" Framing control FSM.
|
""" Framing control FSM.
|
|
|
SOF -- start-of-frame output bit
|
SOF -- start-of-frame output bit
|
state -- FramerState output
|
state -- FramerState output
|
syncFlag -- sync pattern found indication input
|
syncFlag -- sync pattern found indication input
|
clk -- clock input
|
clk -- clock input
|
reset_n -- active low reset
|
reset_n -- active low reset
|
|
|
"""
|
"""
|
|
|
index = Signal(intbv(0)[8:]) # position in frame
|
index = Signal(intbv(0)[8:]) # position in frame
|
|
|
@always(clk.posedge, reset_n.negedge)
|
@always(clk.posedge, reset_n.negedge)
|
def FSM():
|
def FSM():
|
if reset_n == ACTIVE_LOW:
|
if reset_n == ACTIVE_LOW:
|
SOF.next = 0
|
SOF.next = 0
|
index.next = 0
|
index.next = 0
|
state.next = t_State.SEARCH
|
state.next = t_State.SEARCH
|
else:
|
else:
|
index.next = (index + 1) % FRAME_SIZE
|
index.next = (index + 1) % FRAME_SIZE
|
SOF.next = 0
|
SOF.next = 0
|
if state == t_State.SEARCH:
|
if state == t_State.SEARCH:
|
index.next = 1
|
index.next = 1
|
if syncFlag:
|
if syncFlag:
|
state.next = t_State.CONFIRM
|
state.next = t_State.CONFIRM
|
elif state == t_State.CONFIRM:
|
elif state == t_State.CONFIRM:
|
if index == 0:
|
if index == 0:
|
if syncFlag:
|
if syncFlag:
|
state.next = t_State.SYNC
|
state.next = t_State.SYNC
|
else:
|
else:
|
state.next = t_State.SEARCH
|
state.next = t_State.SEARCH
|
elif state == t_State.SYNC:
|
elif state == t_State.SYNC:
|
if index == 0:
|
if index == 0:
|
if not syncFlag:
|
if not syncFlag:
|
state.next = t_State.SEARCH
|
state.next = t_State.SEARCH
|
SOF.next = (index == FRAME_SIZE-1)
|
SOF.next = (index == FRAME_SIZE-1)
|
else:
|
else:
|
raise ValueError("Undefined state")
|
raise ValueError("Undefined state")
|
|
|
return FSM
|
return FSM
|
|
|
SOF = Signal(bool(0))
|
SOF = Signal(bool(0))
|
syncFlag = Signal(bool(0))
|
syncFlag = Signal(bool(0))
|
clk = Signal(bool(0))
|
clk = Signal(bool(0))
|
reset_n = Signal(bool(1))
|
reset_n = Signal(bool(1))
|
state = Signal(t_State.SEARCH)
|
state = Signal(t_State.SEARCH)
|
toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
|
toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
|
toVHDL(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
|
toVHDL(FramerCtrl, SOF, state, syncFlag, clk, reset_n)
|
|
|