----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 07:41:47 12/14/2010
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-- Create Date: 07:41:47 12/14/2010
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-- Design Name:
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-- Design Name:
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-- Module Name: Cache - Rtl
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-- Module Name: Cache - Rtl
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE, work;
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library IEEE, work;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use work.global.all;
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use work.global.all;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity Cache is
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entity Cache is
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generic( constant blocksizeld: integer := 11;
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generic( constant blocksizeld: integer := 11;
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constant ldways: integer := 1;
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constant ldways: integer := 1;
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constant ldCachedWords: integer := 2);
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constant ldCachedWords: integer := 2);
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port( nReset: in std_ulogic; -- System reset active low
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port( nReset: in std_ulogic; -- System reset active low
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Clock: in std_ulogic; -- System Clock
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Clock: in std_ulogic; -- System Clock
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AddressIn: in std_ulogic_vector(RAMrange'high + 1 downto 0); -- Address of memory fetch
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AddressIn: in std_ulogic_vector(RAMrange'high + 1 downto 0); -- Address of memory fetch
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DataIn: in std_ulogic_vector( 31 downto 0); -- Data to write
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DataIn: in std_ulogic_vector( 31 downto 0); -- Data to write
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IOCode: in std_ulogic_vector(2 downto 0); -- operation
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IOCode: in std_ulogic_vector(2 downto 0); -- operation
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-- Bit
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-- Bit
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-- 2 0 read
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-- 2 0 read
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-- 1 write
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-- 1 write
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-- 1 0 11 word
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-- 1 0 11 word
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-- 10 halfword
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-- 10 halfword
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-- 01 single byte
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-- 01 single byte
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-- 00 no operation
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-- 00 no operation
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DataOut: out std_ulogic_vector( 31 downto 0); -- Data read
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DataOut: out std_ulogic_vector( 31 downto 0); -- Data read
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done: out std_ulogic;
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done: out std_ulogic;
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-- memory interface
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-- memory interface
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AddressOut: out std_ulogic_vector(RAMrange'high downto 0); -- memory address
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AddressOut: out std_ulogic_vector(RAMrange'high downto 0); -- memory address
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DataBlockIn: in std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data from memory
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DataBlockIn: in std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data from memory
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reads: out std_ulogic; -- read memory
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reads: out std_ulogic; -- read memory
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DataBlockOut: out std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data to memory
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DataBlockOut: out std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data to memory
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Mask: out std_ulogic_vector( 2 ** ldCachedWords * 4 - 1 downto 0); -- enables for each byte active low
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Mask: out std_ulogic_vector( 2 ** ldCachedWords * 4 - 1 downto 0); -- enables for each byte active low
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writes: out std_ulogic; -- write memory
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writes: out std_ulogic; -- write memory
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ack: in std_ulogic -- acknowledge from memory
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ack: in std_ulogic -- acknowledge from memory
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);
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);
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end Cache;
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end Cache;
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architecture Rtl of Cache is
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architecture Rtl of Cache is
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constant ways: integer := 2 ** ldways;
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constant ways: integer := 2 ** ldways;
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constant ldram: integer := blocksizeld + ldways - 1;
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constant ldram: integer := blocksizeld + ldways - 1;
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constant ldqueuelength: integer := ldram;
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constant ldqueuelength: integer := ldram;
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type IOType is ( Start, busy);
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type IOType is ( Start, busy);
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type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished);
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type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished);
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type rType is ( raminit, ramstart, ramread, ramread1, ramupdate,
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type rType is ( raminit, ramstart, ramread, ramread1, ramupdate,
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ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1);
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ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1);
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type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim);
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type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim);
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subtype myint is natural range 15 downto 0;
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subtype myint is natural range 15 downto 0;
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type TagRAMType is record
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type TagRAMType is record
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cacheAddr: std_ulogic_vector( ldram - 1 downto 0);
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cacheAddr: std_ulogic_vector( ldram - 1 downto 0);
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cacheValid: std_ulogic;
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cacheValid: std_ulogic;
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Tag: std_ulogic_vector( RAMrange'high downto 2 + ldCachedWords + blocksizeld);
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Tag: std_ulogic_vector( RAMrange'high downto 2 + ldCachedWords + blocksizeld);
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TagValid: std_ulogic;
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TagValid: std_ulogic;
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end record;
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end record;
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type WordType is record
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type WordType is record
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Word: std_ulogic_vector(31 downto 0);
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Word: std_ulogic_vector(31 downto 0);
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Modified: std_ulogic_vector( 3 downto 0);
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Modified: std_ulogic_vector( 3 downto 0);
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end record;
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end record;
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type WordArray is array ( 2 ** ldCachedWords - 1 downto 0) of WordType;
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type WordArray is array ( 2 ** ldCachedWords - 1 downto 0) of WordType;
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type CacheType is record
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type CacheType is record
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Words: WordArray;
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Words: WordArray;
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FiFoaddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
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FiFoaddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
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Am: std_ulogic; -- redifined and renamed
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Am: std_ulogic; -- redifined and renamed
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end record;
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end record;
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type FiFoType is record
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type FiFoType is record
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Word: std_ulogic_vector( blocksizeld - 1 downto 0);
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Word: std_ulogic_vector( blocksizeld - 1 downto 0);
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way: std_ulogic_vector( ldways downto 0);
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way: std_ulogic_vector( ldways downto 0);
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valid: std_ulogic;
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valid: std_ulogic;
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end record;
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end record;
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type TagRAMarray is array ( ways - 1 downto 0) of TagRAMType;
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type TagRAMarray is array ( ways - 1 downto 0) of TagRAMType;
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type TagBuffer is array ( ways - 1 downto 0) of std_ulogic_vector( RAMrange'high - ldCachedWords - blocksizeld - 2 + ldram + 2 downto 0);
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type TagBuffer is array ( ways - 1 downto 0) of std_ulogic_vector( RAMrange'high - ldCachedWords - blocksizeld - 2 + ldram + 2 downto 0);
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type TagFile is array ( 2 ** blocksizeld - 1 downto 0) of std_ulogic_vector( RAMrange'high - ldCachedWords - blocksizeld - 2 + ldram + 2 downto 0);
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type TagFile is array ( 2 ** blocksizeld - 1 downto 0) of std_ulogic_vector( RAMrange'high - ldCachedWords - blocksizeld - 2 + ldram + 2 downto 0);
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type TagFiles is array ( ways - 1 downto 0) of TagFile;
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type TagFiles is array ( ways - 1 downto 0) of TagFile;
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type RAMFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( 35 downto 0);
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type RAMFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( 35 downto 0);
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type RAMFiles is array ( 2 ** ldCachedWords - 1 downto 0) of RAMFile;
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type RAMFiles is array ( 2 ** ldCachedWords - 1 downto 0) of RAMFile;
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type RAMBuffer is array ( 2 ** ldCachedWords - 1 downto 0) of std_ulogic_vector( 35 downto 0);
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type RAMBuffer is array ( 2 ** ldCachedWords - 1 downto 0) of std_ulogic_vector( 35 downto 0);
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type AFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldqueuelength downto 0); -- redimensioned
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type AFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldqueuelength downto 0); -- redimensioned
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type myarrayf is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldram - 1 downto 0);
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type myarrayf is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldram - 1 downto 0);
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type myarrayA is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( blocksizeld + ldways + 1 downto 0);
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type myarrayA is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( blocksizeld + ldways + 1 downto 0);
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signal RAMs: RAMFiles;
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signal RAMs: RAMFiles;
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signal Ax: AFile;
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signal Ax: AFile;
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signal tagRAM: TagFiles;
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signal tagRAM: TagFiles;
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signal tagdummy, tagBuff, TagRAMIn, TagRAMOut: TagRAMarray;
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signal tagdummy, tagBuff, TagRAMIn, TagRAMOut: TagRAMarray;
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signal RecBuff, CacheIn, CacheOut: CacheType;
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signal RecBuff, CacheIn, CacheOut: CacheType;
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signal blockIn, blockOut: WordArray;
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signal blockIn, blockOut: WordArray;
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signal DataInh: std_ulogic_vector( 31 downto 0);
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signal DataInh: std_ulogic_vector( 31 downto 0);
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signal A1In, A1Out, AmIn, AmOut: FiFoType;
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signal A1In, A1Out, AmIn, AmOut: FiFoType;
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signal putA1, removeA1, getA1, emptyA1, fullA1: std_ulogic;
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signal putA1, removeA1, getA1, emptyA1, fullA1: std_ulogic;
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signal putAm, removeAm, getAm, emptyAm, fullAm: std_ulogic;
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signal putAm, removeAm, getAm, emptyAm, fullAm: std_ulogic;
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signal A1Inaddr, A1Outaddr, AmInaddr, AmOutaddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
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signal A1Inaddr, A1Outaddr, AmInaddr, AmOutaddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
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signal emptyf, getf, putf: std_ulogic;
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signal emptyf, getf, putf: std_ulogic;
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signal cindex, FreeOut, FreeIn: std_ulogic_vector( ldram - 1 downto 0);
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signal cindex, FreeOut, FreeIn: std_ulogic_vector( ldram - 1 downto 0);
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signal ramf: myarrayf;
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signal ramf: myarrayf;
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signal counterf: unsigned( ldram downto 0);
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signal counterf: unsigned( ldram downto 0);
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signal firstf, lastf: unsigned( ldram - 1 downto 0);
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signal firstf, lastf: unsigned( ldram - 1 downto 0);
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signal newFiFoAddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
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signal newFiFoAddr: std_ulogic_vector( ldqueuelength - 1 downto 0);
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signal newAm: std_ulogic; -- redifined and renamed
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signal newAm: std_ulogic; -- redifined and renamed
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signal initcount: unsigned( blocksizeld - 1 downto 0);
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signal initcount: unsigned( blocksizeld - 1 downto 0);
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signal initcount1: unsigned( ldram - 1 downto 0);
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signal initcount1: unsigned( ldram - 1 downto 0);
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signal ramA1: myarrayA;
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signal ramA1: myarrayA;
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signal counterA1: unsigned( ldqueuelength downto 0);
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signal counterA1: unsigned( ldqueuelength downto 0);
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signal firstA1, lastA1: unsigned( ldqueuelength - 1 downto 0);
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signal firstA1, lastA1: unsigned( ldqueuelength - 1 downto 0);
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signal ramAm: myarrayA;
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signal ramAm: myarrayA;
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signal counterAm: unsigned( ldqueuelength downto 0);
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signal counterAm: unsigned( ldqueuelength downto 0);
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signal firstAm, lastAm: unsigned( ldqueuelength - 1 downto 0);
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signal firstAm, lastAm: unsigned( ldqueuelength - 1 downto 0);
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signal AddressInh: std_ulogic_vector( AddressIn'high -1 downto 0);
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signal AddressInh: std_ulogic_vector( AddressIn'high -1 downto 0);
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signal IOCodeh: std_ulogic_vector( IOCode'range);
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signal IOCodeh: std_ulogic_vector( IOCode'range);
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signal toFlush, AddressInt: std_ulogic_vector( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
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signal toFlush, AddressInt: std_ulogic_vector( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
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signal found, free, elim, del: myint;
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signal found, free, elim, del: myint;
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signal stateIO: IOType;
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signal stateIO: IOType;
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signal statetag: tType;
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signal statetag: tType;
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signal stateram: rType;
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signal stateram: rType;
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signal statequeue: fType;
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signal statequeue: fType;
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag,
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag, flag1,
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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signal gal: std_ulogic_vector( 7 downto 0);
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signal gal: std_ulogic_vector( 7 downto 0);
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begin
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begin
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blockIO: process( nReset, Clock, readb, writeb) is
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blockIO: process( nReset, Clock, readb, writeb) is
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variable s: std_ulogic;
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variable s: std_ulogic;
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begin
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begin
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if nReset /= '1' then
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if nReset /= '1' then
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writesh <= '0';
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writesh <= '0';
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readsh <= '0';
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readsh <= '0';
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stateIO <= start;
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stateIO <= start;
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elsif rising_edge(Clock) then
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elsif rising_edge(Clock) then
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case stateIO is
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case stateIO is
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when start =>
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when start =>
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if readb = '1' then
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if readb = '1' then
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Mask <= ( others => '1');
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Mask <= ( others => '1');
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readsh <= '1';
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readsh <= '1';
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stateIO <= busy;
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stateIO <= busy;
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elsif writeb = '1' then
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elsif writeb = '1' then
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s := '0';
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s := '0';
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for i in blockOut'range loop
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for i in blockOut'range loop
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DataBlockOut( ( i + 1) * 32 - 1 downto i * 32) <= blockOut( i).word;
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DataBlockOut( ( i + 1) * 32 - 1 downto i * 32) <= blockOut( i).word;
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Mask( ( i + 1) * 4 - 1 downto i * 4) <= not blockOut( i).Modified;
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Mask( ( i + 1) * 4 - 1 downto i * 4) <= not blockOut( i).Modified;
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s := s or blockOut( i).Modified(0) or blockOut( i).Modified(1) or
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s := s or blockOut( i).Modified(0) or blockOut( i).Modified(1) or
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blockOut( i).Modified(2) or blockOut( i).Modified(3);
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blockOut( i).Modified(2) or blockOut( i).Modified(3);
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end loop;
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end loop;
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writesh <= s;
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writesh <= s;
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if s = '1' then
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if s = '1' then
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stateIO <= busy;
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stateIO <= busy;
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end if;
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end if;
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end if;
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end if;
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when busy =>
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when busy =>
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if ack = '1' then
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if ack = '1' then
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stateIO <= start;
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stateIO <= start;
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if readsh = '1' then
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if readsh = '1' then
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for i in blockIn'range loop
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for i in blockIn'range loop
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blockIn( i).word <= DataBlockIn( ( i + 1) * 32 - 1 downto i * 32);
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blockIn( i).word <= DataBlockIn( ( i + 1) * 32 - 1 downto i * 32);
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blockIn( i).Modified <= ( others => '0');
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blockIn( i).Modified <= ( others => '0');
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end loop;
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end loop;
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end if;
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end if;
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readsh <= '0';
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readsh <= '0';
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writesh <= '0';
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writesh <= '0';
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process blockIO;
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end process blockIO;
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writes <= writesh;
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writes <= writesh;
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reads <= readsh;
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reads <= readsh;
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tagrams: process ( nReset, Clock) is
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tagrams: process ( nReset, Clock) is
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variable a, b, d: myint;
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variable a, b, d: myint;
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variable DataInTag, DataOutTag: TagBuffer;
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variable DataInTag, DataOutTag: TagBuffer;
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begin
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begin
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if rising_edge(Clock) then
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if rising_edge(Clock) then
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if nReset /= '1' then
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if nReset /= '1' then
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statetag <= inittag;
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statetag <= inittag;
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writet <= '0';
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writet <= '0';
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enableram <= '0';
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enableram <= '0';
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oldint <= '0';
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oldint <= '0';
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found <= 15;
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found <= 15;
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free <= 15;
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free <= 15;
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done <= '0'; -- NEW
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done <= '0'; -- NEW
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initcount <= ( others => '0');
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initcount <= ( others => '0');
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AddressInt <= ( others => '0');
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AddressInt <= ( others => '0');
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IOCodeh <= ( others => '0');
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IOCodeh <= ( others => '0');
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AddressInh <= ( others => '0');
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AddressInh <= ( others => '0');
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gal <= ( others => '1');
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gal <= ( others => '1');
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else
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else
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gal <= gal( 6 downto 4) & ( gal( 3) xor gal( 7)) & ( gal( 2) xor gal( 7)) & ( gal( 1) xor gal( 7)) & gal( 0) & gal( 7);
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gal <= gal( 6 downto 4) & ( gal( 3) xor gal( 7)) & ( gal( 2) xor gal( 7)) & ( gal( 1) xor gal( 7)) & gal( 0) & gal( 7);
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oldint <= interrupt;
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oldint <= interrupt;
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case statetag is
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case statetag is
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when inittag =>
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when inittag =>
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for i in tagRAMIn'range loop
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for i in tagRAMIn'range loop
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tagRAMIn(i).tagValid <= '0';
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tagRAMIn(i).tagValid <= '0';
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tagRAMIn(i).tag <= ( others => '0');
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tagRAMIn(i).tag <= ( others => '0');
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tagRAMIn(i).cacheValid <= '0';
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tagRAMIn(i).cacheValid <= '0';
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tagRAMIn(i).cacheAddr <= ( others => '0');
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tagRAMIn(i).cacheAddr <= ( others => '0');
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end loop;
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end loop;
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AddressInt <= std_ulogic_vector(initcount);
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AddressInt <= std_ulogic_vector(initcount);
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initcount <= initcount + 1;
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initcount <= initcount + 1;
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if unsigned( not AddressInt) = 0 then
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if unsigned( not AddressInt) = 0 then
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statetag <= startt;
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statetag <= startt;
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writet <= '0';
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writet <= '0';
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else
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else
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writet <= '1';
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writet <= '1';
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end if;
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end if;
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when startt =>
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when startt =>
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if IOCode( 1 downto 0) /= "00" and AddressIn( AddressIn'high) = '0' then
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if IOCode( 1 downto 0) /= "00" and AddressIn( AddressIn'high) = '0' then
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-- request encountered
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-- request encountered
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AddressInh <= AddressIn(AddressInh'range);
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AddressInh <= AddressIn(AddressInh'range);
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IOCodeh <= IOCode;
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IOCodeh <= IOCode;
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AddressInt <= AddressIn( AddressInt'range);
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AddressInt <= AddressIn( AddressInt'range);
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DataInh <= DataIn;
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DataInh <= DataIn;
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statetag <= startt1;
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statetag <= startt1;
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end if;
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end if;
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when startt1 =>
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when startt1 =>
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statetag <= tagtest;
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statetag <= tagtest;
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when tagtest =>
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when tagtest =>
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a := 15;
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a := 15;
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b := 15;
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b := 15;
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for i in 0 to TagRAMarray'high loop
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for i in 0 to TagRAMarray'high loop
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if tagRAMOut( i).tagValid = '1' then
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if tagRAMOut( i).tagValid = '1' then
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if AddressInh(tagRAMout( i).tag'range) = tagRAMout( i).tag then
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if AddressInh(tagRAMout( i).tag'range) = tagRAMout( i).tag then
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a := i; -- present
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a := i; -- present
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end if;
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end if;
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else
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else
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b := i; -- free entry
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b := i; -- free entry
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end if;
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end if;
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end loop;
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end loop;
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found <= a;
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found <= a;
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free <= b;
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free <= b;
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if ways = 1 then
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if ways = 1 then
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elim <= 0;
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elim <= 0;
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else
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else
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elim <= to_integer( gal( ldways - 1 downto 0));
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elim <= to_integer( gal( ldways - 1 downto 0));
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end if;
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end if;
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if stateram = ramstart then
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if stateram = ramstart then
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enableram <= '1';
|
enableram <= '1';
|
statetag <= tagwait;
|
statetag <= tagwait;
|
end if;
|
end if;
|
when tagwait =>
|
when tagwait =>
|
writet <= '0';
|
writet <= '0';
|
|
|
if interrupt = '1' and oldint = '0' then
|
if interrupt = '1' and oldint = '0' then
|
enableram <= '0';
|
enableram <= '0';
|
AddressInt <= toFlush;
|
AddressInt <= toFlush;
|
statetag <= stateget;
|
statetag <= stateget;
|
elsif queuedone = '1' then
|
elsif queuedone = '1' then
|
enableram <= '0';
|
enableram <= '0';
|
statetag <= finish;
|
statetag <= finish;
|
end if;
|
end if;
|
when stateget =>
|
when stateget =>
|
statetag <= stateget1;
|
statetag <= stateget1;
|
when stateget1 =>
|
when stateget1 =>
|
enableram <= '1';
|
enableram <= '1';
|
tagDummy <= tagRAMOut;
|
tagDummy <= tagRAMOut;
|
|
|
for i in tagRAMIn'range loop
|
for i in tagRAMIn'range loop
|
if del = i then
|
if del = i then
|
tagRAMIn( i).tagvalid <= '0';
|
tagRAMIn( i).tagvalid <= '0';
|
tagRAMIn( i).cacheValid <= '0';
|
tagRAMIn( i).cacheValid <= '0';
|
tagRAMIn( i).tag <= ( others => '0');
|
tagRAMIn( i).tag <= ( others => '0');
|
tagRAMIn( i).cacheAddr <= ( others => '0');
|
tagRAMIn( i).cacheAddr <= ( others => '0');
|
writet <= '1';
|
writet <= '1';
|
else
|
else
|
tagRAMIn( i) <= tagRAMOut( i);
|
tagRAMIn( i) <= tagRAMOut( i);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
statetag <= tagwait;
|
statetag <= tagwait;
|
when finish =>
|
when finish =>
|
if doneh = '1' then
|
if doneh = '1' then
|
tagRAMIn <= tagBuff;
|
tagRAMIn <= tagBuff;
|
writet <= '1';
|
writet <= '1';
|
AddressInt <= AddressInh( AddressInt'range);
|
AddressInt <= AddressInh( AddressInt'range);
|
done <= '1';
|
done <= '1';
|
statetag <= finished;
|
statetag <= finished;
|
end if;
|
end if;
|
when finished => -- NEW
|
when finished => -- NEW
|
writet <= '0';
|
writet <= '0';
|
done <= '0';
|
done <= '0';
|
statetag <= startt;
|
statetag <= startt;
|
end case;
|
end case;
|
|
|
for i in tagRAM'range loop
|
for i in tagRAM'range loop
|
DataInTag( i) := TagRAMIn( i).TagValid & TagRAMIn( i).Tag & TagRAMIn( i).cacheValid & TagRAMIn( i).cacheAddr;
|
DataInTag( i) := TagRAMIn( i).TagValid & TagRAMIn( i).Tag & TagRAMIn( i).cacheValid & TagRAMIn( i).cacheAddr;
|
|
|
if writet = '1' then
|
if writet = '1' then
|
tagRAM(i)(to_integer( AddressInt)) <= DataInTag( i);
|
tagRAM(i)(to_integer( AddressInt)) <= DataInTag( i);
|
else
|
else
|
DataOutTag( i) := tagRAM(i)(to_integer( AddressInt));
|
DataOutTag( i) := tagRAM(i)(to_integer( AddressInt));
|
|
|
TagRAMOut( i).cacheAddr <= DataOutTag( i)( ldram - 1 downto 0);
|
TagRAMOut( i).cacheAddr <= DataOutTag( i)( ldram - 1 downto 0);
|
TagRAMOut( i).cacheValid <= DataOutTag( i)( ldram);
|
TagRAMOut( i).cacheValid <= DataOutTag( i)( ldram);
|
TagRAMOut( i).Tag <= DataOutTag( i)( DataOutTag( 0)'high - 1 downto ldram + 1);
|
TagRAMOut( i).Tag <= DataOutTag( i)( DataOutTag( 0)'high - 1 downto ldram + 1);
|
TagRAMOut( i).TagValid <= DataOutTag( i)( DataOutTag( 0)'high);
|
TagRAMOut( i).TagValid <= DataOutTag( i)( DataOutTag( 0)'high);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end if;
|
end if;
|
end Process tagrams;
|
end Process tagrams;
|
|
|
dataram: process (nReset, Clock, enableram) is
|
dataram: process (nReset, Clock, enableram) is
|
variable en, acc, hi: std_ulogic;
|
variable en, acc, hi: std_ulogic;
|
variable f, g: std_ulogic_vector( CacheIn.FiFoAddr'length downto 0);
|
variable f, g: std_ulogic_vector( CacheIn.FiFoAddr'length downto 0);
|
variable a, b: RAMBuffer;
|
variable a, b: RAMBuffer;
|
variable index, index1: integer;
|
variable index, index1: integer;
|
|
|
variable address: std_ulogic_vector( ldram - 1 downto 0);
|
variable address: std_ulogic_vector( ldram - 1 downto 0);
|
variable uaddress: unsigned( ldram - 1 downto 0);
|
variable uaddress: unsigned( ldram - 1 downto 0);
|
variable datum: std_ulogic_vector( FreeIn'range);
|
variable datum: std_ulogic_vector( FreeIn'range);
|
variable w: std_ulogic;
|
variable w: std_ulogic;
|
begin
|
begin
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
if nReset /= '1' then
|
if nReset /= '1' then
|
enablequeue <= '0';
|
enablequeue <= '0';
|
stateram <= raminit;
|
stateram <= raminit;
|
writec <= '0';
|
writec <= '0';
|
writeb <= '0';
|
writeb <= '0';
|
readb <= '0';
|
readb <= '0';
|
getf <= '0';
|
getf <= '0';
|
putf <= '0'; -- NEW inserted
|
putf <= '0'; -- NEW inserted
|
doneh <= '0';
|
doneh <= '0';
|
accinterrupt <= '0';
|
accinterrupt <= '0';
|
accqueue <= '0';
|
accqueue <= '0';
|
isfull <= '0';
|
isfull <= '0';
|
flag <= '0';
|
flag <= '0';
|
|
flag1 <= '1';
|
initcount1 <= ( others => '0');
|
initcount1 <= ( others => '0');
|
FreeIn <= ( others => '0');
|
FreeIn <= ( others => '0');
|
firstf <= ( others => '0');
|
firstf <= ( others => '0');
|
lastf <= ( others => '0');
|
lastf <= ( others => '0');
|
counterf <= ( others => '0');
|
counterf <= ( others => '0');
|
else
|
else
|
hi := accinterrupt or (interrupt and not oldint);
|
hi := accinterrupt or (interrupt and not oldint);
|
acc := accqueue or queuedone;
|
acc := accqueue or queuedone;
|
en := enablequeue and not acc;
|
en := enablequeue and not acc;
|
|
|
if ldCachedWords = 0 then
|
if ldCachedWords = 0 then
|
index := 0;
|
index := 0;
|
else
|
else
|
index := to_integer( AddressInh( ldCachedWords + 1 downto 2));
|
index := to_integer( AddressInh( ldCachedWords + 1 downto 2));
|
end if;
|
end if;
|
|
|
case stateram is
|
case stateram is
|
when raminit =>
|
when raminit =>
|
FreeIn <= std_ulogic_vector( initcount1);
|
FreeIn <= std_ulogic_vector( initcount1);
|
initcount1 <= initcount1 + 1;
|
initcount1 <= initcount1 + 1;
|
|
|
if unsigned( not FreeIn) = 0 then
|
if unsigned( not FreeIn) = 0 then
|
stateram <= ramstart;
|
stateram <= ramstart;
|
putf <= '0';
|
putf <= '0';
|
else
|
else
|
putf <= '1';
|
putf <= '1';
|
end if;
|
end if;
|
when ramstart =>
|
when ramstart =>
|
if enableram = '1' then -- UPDATE
|
if enableram = '1' then -- UPDATE
|
if isfull = '0' then
|
if isfull = '0' then
|
tagBuff <= tagRAMOut;
|
tagBuff <= tagRAMOut;
|
end if;
|
end if;
|
if found /= 15 then
|
if found /= 15 then
|
|
tagBuff <= tagRAMOut;
|
cindex <= tagRAMOut( found).cacheAddr;
|
cindex <= tagRAMOut( found).cacheAddr;
|
isfull <= '0';
|
isfull <= '0';
|
stateram <= ramupdate;
|
stateram <= ramupdate;
|
elsif free /= 15 then
|
elsif free /= 15 then
|
en := '1';
|
en := '1';
|
if emptyf = '1' and isfull = '0' then
|
if emptyf = '1' and isfull = '0' then
|
isfull <= '1';
|
isfull <= '1';
|
|
tagBuff <= tagRAMOut;
|
stateram <= ramwait;
|
stateram <= ramwait;
|
else
|
else
|
cindex <= FreeOut;
|
cindex <= FreeOut;
|
if isfull = '1' then
|
if isfull = '1' then
|
tagBuff( free).cacheAddr <= FreeOut;
|
tagBuff( free).cacheAddr <= FreeOut;
|
tagBuff( free).cacheValid <= '1';
|
tagBuff( free).cacheValid <= '1';
|
tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
|
tagBuff( free).tag <= AddressInh( tagBuff( free).tag'range);
|
tagBuff( free).tagValid <= '1';
|
tagBuff( free).tagValid <= '1';
|
else
|
else
|
tagRAMOut( free).cacheAddr <= FreeOut;
|
tagRAMOut( free).cacheAddr <= FreeOut;
|
tagRAMOut( free).cacheValid <= '1';
|
tagRAMOut( free).cacheValid <= '1';
|
tagRAMOut( free).tag <= AddressInh( tagRAMOut( free).tag'range);
|
tagRAMOut( free).tag <= AddressInh( tagRAMOut( free).tag'range);
|
tagRAMOut( free).tagValid <= '1';
|
tagRAMOut( free).tagValid <= '1';
|
|
flag1 <= '1';
|
end if;
|
end if;
|
isfull <= '0';
|
isfull <= '0';
|
getf <= '1';
|
getf <= '1';
|
if IOCodeh = "111" and ldCachedWords = 0 then
|
if IOCodeh = "111" and ldCachedWords = 0 then
|
stateram <= ramupdate2;
|
stateram <= ramupdate2;
|
else
|
else
|
readb <= '1';
|
readb <= '1';
|
AddressOut <= AddressInh( AddressOut'range);
|
AddressOut <= AddressInh( AddressOut'range);
|
stateram <= ramread;
|
stateram <= ramread;
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
else
|
cindex <= tagRAMOut( elim).cacheAddr;
|
cindex <= tagRAMOut( elim).cacheAddr;
|
isfull <= '0';
|
isfull <= '0';
|
stateram <= ramupdate;
|
stateram <= ramupdate;
|
end if;
|
end if;
|
end if;
|
end if;
|
when ramupdate =>
|
when ramupdate =>
|
stateram <= ramupdate1;
|
stateram <= ramupdate1;
|
when ramupdate1 =>
|
when ramupdate1 =>
|
cacheIn <= cacheOut;
|
cacheIn <= cacheOut;
|
blockOut <= cacheOut.Words;
|
blockOut <= cacheOut.Words;
|
RecBuff <= cacheOut;
|
RecBuff <= cacheOut;
|
en := '1';
|
en := '1';
|
if found /= 15 then
|
if found /= 15 then
|
stateram <= ramupdate2;
|
stateram <= ramupdate2;
|
else
|
else
|
AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
|
AddressOut <= tagBuff( elim).tag & AddressInh( AddressInt'range) & ( ldCachedWords + 1 downto 0 => '0');
|
writeb <= '1';
|
writeb <= '1';
|
flag <= '1';
|
flag <= '1';
|
stateram <= ramflush;
|
stateram <= ramflush;
|
end if;
|
end if;
|
when ramwait =>
|
when ramwait =>
|
if hi = '1' then
|
if hi = '1' then
|
stateram <= ramwait1;
|
stateram <= ramwait1;
|
end if;
|
end if;
|
when ramwait1 =>
|
when ramwait1 =>
|
writec <= '0';
|
writec <= '0';
|
|
|
if del /= 15 and enableram = '1' then
|
if del /= 15 and enableram = '1' then
|
if toflush = AddressInh( toflush'range) then -- inserted, tagline could match flushing tagline !!!!
|
if toflush = AddressInh( toflush'range) then -- inserted, tagline could match flushing tagline !!!!
|
tagBuff( del).tagvalid <= '0';
|
tagBuff( del).tagvalid <= '0';
|
tagBuff( del).cacheValid <= '0';
|
tagBuff( del).cacheValid <= '0';
|
tagBuff( del).tag <= ( others => '0');
|
tagBuff( del).tag <= ( others => '0');
|
tagBuff( del).cacheAddr <= ( others => '0');
|
tagBuff( del).cacheAddr <= ( others => '0');
|
end if;
|
end if;
|
cindex <= tagdummy( del).cacheAddr;
|
cindex <= tagdummy( del).cacheAddr;
|
FreeIn <= tagdummy( del).cacheAddr;
|
FreeIn <= tagdummy( del).cacheAddr;
|
putf <= tagdummy( del).cacheValid;
|
putf <= tagdummy( del).cacheValid;
|
stateram <= ramclean;
|
stateram <= ramclean;
|
end if;
|
end if;
|
when ramread =>
|
when ramread =>
|
readb <= '0';
|
readb <= '0';
|
getf <= '0';
|
getf <= '0';
|
|
if flag1 = '1' then
|
|
tagBuff <= tagRAMOut;
|
|
flag1 <= '0';
|
|
end if;
|
stateram <= ramread1;
|
stateram <= ramread1;
|
when ramread1 =>
|
when ramread1 =>
|
if readsh = '0' then
|
if readsh = '0' then
|
for i in blockIn'range loop
|
for i in blockIn'range loop
|
cacheIn.Words( i) <= blockIn( i);
|
cacheIn.Words( i) <= blockIn( i);
|
end loop;
|
end loop;
|
stateram <= ramupdate2;
|
stateram <= ramupdate2;
|
end if;
|
end if;
|
when ramupdate2 =>
|
when ramupdate2 =>
|
|
if flag1 = '1' then
|
|
tagBuff <= tagRAMOut;
|
|
flag1 <= '0';
|
|
end if;
|
if IOCodeh(2) = '1' then
|
if IOCodeh(2) = '1' then
|
if IOCodeh(1) = '1' then
|
if IOCodeh(1) = '1' then
|
If IOCodeh(0) = '1' then
|
If IOCodeh(0) = '1' then
|
cacheIn.Words( index).Word <= DataInh;
|
cacheIn.Words( index).Word <= DataInh;
|
cacheIn.Words( index).Modified <= "1111";
|
cacheIn.Words( index).Modified <= "1111";
|
elsif AddressInh(1) = '1' then
|
elsif AddressInh(1) = '1' then
|
cacheIn.Words( index).Word( 31 downto 16) <= DataInh( 15 downto 0);
|
cacheIn.Words( index).Word( 31 downto 16) <= DataInh( 15 downto 0);
|
cacheIn.Words( index).Modified( 3 downto 2) <= "11";
|
cacheIn.Words( index).Modified( 3 downto 2) <= "11";
|
else
|
else
|
cacheIn.Words( index).Word( 15 downto 0) <= DataInh( 15 downto 0);
|
cacheIn.Words( index).Word( 15 downto 0) <= DataInh( 15 downto 0);
|
cacheIn.Words( index).Modified( 1 downto 0) <= "11";
|
cacheIn.Words( index).Modified( 1 downto 0) <= "11";
|
end if;
|
end if;
|
else
|
else
|
if AddressInh(1) = '0' then
|
if AddressInh(1) = '0' then
|
if AddressInh(0) = '0' then
|
if AddressInh(0) = '0' then
|
cacheIn.Words( index).Word( 7 downto 0) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Word( 7 downto 0) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Modified(0) <= '1';
|
cacheIn.Words( index).Modified(0) <= '1';
|
else
|
else
|
cacheIn.Words( index).Word( 15 downto 8) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Word( 15 downto 8) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Modified(1) <= '1';
|
cacheIn.Words( index).Modified(1) <= '1';
|
end if;
|
end if;
|
else
|
else
|
if AddressInh(0) = '0' then
|
if AddressInh(0) = '0' then
|
cacheIn.Words( index).Word( 23 downto 16) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Word( 23 downto 16) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Modified(2) <= '1';
|
cacheIn.Words( index).Modified(2) <= '1';
|
else
|
else
|
cacheIn.Words( index).Word( 31 downto 24) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Word( 31 downto 24) <= DataInh( 7 downto 0);
|
cacheIn.Words( index).Modified(3) <= '1';
|
cacheIn.Words( index).Modified(3) <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
else
|
DataOut <= cacheIn.Words( index).Word;
|
DataOut <= cacheIn.Words( index).Word;
|
end if;
|
end if;
|
|
|
cacheIn.FiFoAddr <= newFiFoAddr;
|
cacheIn.FiFoAddr <= newFiFoAddr;
|
cacheIn.Am <= newAm;
|
cacheIn.Am <= newAm;
|
|
|
getf <= '0';
|
getf <= '0';
|
writec <= '1';
|
writec <= '1';
|
|
|
if hi = '1' then
|
if hi = '1' then
|
stateram <= ramwait1;
|
stateram <= ramwait1;
|
elsif acc = '1' then
|
elsif acc = '1' then
|
doneh <= '1';
|
doneh <= '1';
|
stateram <= ramupdate3;
|
stateram <= ramupdate3;
|
end if;
|
end if;
|
when ramupdate3 =>
|
when ramupdate3 =>
|
hi := '0';
|
hi := '0';
|
acc := '0';
|
acc := '0';
|
en := '0';
|
en := '0';
|
writec <= '0';
|
writec <= '0';
|
doneh <= '0';
|
doneh <= '0';
|
stateram <= ramstart;
|
stateram <= ramstart;
|
when ramclean =>
|
when ramclean =>
|
putf <= '0';
|
putf <= '0';
|
stateram <= ramclean1;
|
stateram <= ramclean1;
|
when ramclean1 =>
|
when ramclean1 =>
|
if del /= 15 then
|
if del /= 15 then
|
blockOut <= cacheOut.words;
|
blockOut <= cacheOut.words;
|
writeb <= tagdummy( del).tagValid;
|
writeb <= tagdummy( del).tagValid;
|
AddressOut <= tagdummy( del).tag & toFlush & ( ldCachedWords + 1 downto 0 => '0');
|
AddressOut <= tagdummy( del).tag & toFlush & ( ldCachedWords + 1 downto 0 => '0');
|
stateram <= ramflush;
|
stateram <= ramflush;
|
end if;
|
end if;
|
when ramflush =>
|
when ramflush =>
|
writeb <= '0';
|
writeb <= '0';
|
for i in blockIn'range loop
|
for i in blockIn'range loop
|
cacheIn.Words( i).Word <= ( others => '0');
|
cacheIn.Words( i).Word <= ( others => '0');
|
cacheIn.Words( i).Modified <= ( others => '0');
|
cacheIn.Words( i).Modified <= ( others => '0');
|
end loop;
|
end loop;
|
|
|
stateram <= ramflush1;
|
stateram <= ramflush1;
|
when ramflush1 =>
|
when ramflush1 =>
|
if writesh = '0' then
|
if writesh = '0' then
|
if flag = '1' then
|
if flag = '1' then
|
tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
|
tagBuff( elim).tag <= AddressInh( tagBuff( elim).tag'range);
|
tagBuff( elim).tagValid <= '1';
|
tagBuff( elim).tagValid <= '1';
|
flag <= '0';
|
flag <= '0';
|
if IOCodeh = "111" and ldCachedWords = 0 then
|
if IOCodeh = "111" and ldCachedWords = 0 then
|
stateram <= ramupdate2;
|
stateram <= ramupdate2;
|
else
|
else
|
readb <= '1';
|
readb <= '1';
|
AddressOut <= AddressInh( AddressOut'range);
|
AddressOut <= AddressInh( AddressOut'range);
|
stateram <= ramread;
|
stateram <= ramread;
|
end if;
|
end if;
|
elsif isfull = '1' then
|
elsif isfull = '1' then
|
hi := '0';
|
hi := '0';
|
stateram <= ramstart;
|
stateram <= ramstart;
|
elsif acc = '1' then
|
elsif acc = '1' then
|
doneh <= '1';
|
doneh <= '1';
|
stateram <= ramupdate3;
|
stateram <= ramupdate3;
|
end if;
|
end if;
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
accinterrupt <= hi;
|
accinterrupt <= hi;
|
enablequeue <= en;
|
enablequeue <= en;
|
accqueue <= acc;
|
accqueue <= acc;
|
|
|
f := CacheIn.Am & CacheIn.FiFoAddr;
|
f := CacheIn.Am & CacheIn.FiFoAddr;
|
if writec = '1' then
|
if writec = '1' then
|
Ax( to_integer( cindex)) <= f;
|
Ax( to_integer( cindex)) <= f;
|
else
|
else
|
g := Ax( to_integer( cindex));
|
g := Ax( to_integer( cindex));
|
CacheOut.FiFoAddr <= g( g'high - 1 downto g'low);
|
CacheOut.FiFoAddr <= g( g'high - 1 downto g'low);
|
CacheOut.Am <= g( g'high);
|
CacheOut.Am <= g( g'high);
|
end if;
|
end if;
|
|
|
for i in RAMBuffer'range loop
|
for i in RAMBuffer'range loop
|
a( i) := CacheIn.Words( i).Modified & CacheIn.Words( i).Word;
|
a( i) := CacheIn.Words( i).Modified & CacheIn.Words( i).Word;
|
if writec = '1' then
|
if writec = '1' then
|
RAMs( i)( to_integer( cindex)) <= a( i);
|
RAMs( i)( to_integer( cindex)) <= a( i);
|
else
|
else
|
b( i) := RAMs( i)( to_integer( cindex));
|
b( i) := RAMs( i)( to_integer( cindex));
|
CacheOut.Words( i).Word <= b( i)( 31 downto 0);
|
CacheOut.Words( i).Word <= b( i)( 31 downto 0);
|
CacheOut.Words( i).Modified <= b( i)( 35 downto 32);
|
CacheOut.Words( i).Modified <= b( i)( 35 downto 32);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
if putf = '1' then
|
if putf = '1' then
|
address := std_ulogic_vector( firstf);
|
address := std_ulogic_vector( firstf);
|
datum := FreeIn;
|
datum := FreeIn;
|
firstf <= firstf + 1;
|
firstf <= firstf + 1;
|
counterf <= counterf + 1;
|
counterf <= counterf + 1;
|
w := '1';
|
w := '1';
|
else
|
else
|
uaddress := lastf;
|
uaddress := lastf;
|
if getf = '1' and counterf /= 0 then
|
if getf = '1' and counterf /= 0 then
|
counterf <= counterf - 1;
|
counterf <= counterf - 1;
|
uaddress := uaddress + 1;
|
uaddress := uaddress + 1;
|
end if;
|
end if;
|
lastf <= uaddress;
|
lastf <= uaddress;
|
address := std_ulogic_vector( uaddress);
|
address := std_ulogic_vector( uaddress);
|
w := '0';
|
w := '0';
|
end if;
|
end if;
|
|
|
if w = '1' then
|
if w = '1' then
|
ramf( to_integer( address)) <= datum;
|
ramf( to_integer( address)) <= datum;
|
else
|
else
|
FreeOut <= ramf( to_integer( address));
|
FreeOut <= ramf( to_integer( address));
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dataram;
|
end process dataram;
|
|
|
emptyf <= '1' when counterf = 0 else '0';
|
emptyf <= '1' when counterf = 0 else '0';
|
|
|
queues: process( nReset, Clock, enablequeue) is
|
queues: process( nReset, Clock, enablequeue) is
|
variable acc, hi: std_ulogic;
|
variable acc, hi: std_ulogic;
|
variable A1OutBuff, AmOutBuff: std_ulogic_vector( blocksizeld + ldways + 1 downto 0);
|
variable A1OutBuff, AmOutBuff: std_ulogic_vector( blocksizeld + ldways + 1 downto 0);
|
variable addressA1: std_ulogic_vector( ldqueuelength - 1 downto 0);
|
variable addressA1: std_ulogic_vector( ldqueuelength - 1 downto 0);
|
variable diff, uaddressA1: unsigned( ldqueuelength - 1 downto 0);
|
variable diff, uaddressA1: unsigned( ldqueuelength - 1 downto 0);
|
variable datumA1: std_ulogic_vector( A1OutBuff'range);
|
variable datumA1: std_ulogic_vector( A1OutBuff'range);
|
variable wA1: std_ulogic;
|
variable wA1: std_ulogic;
|
variable addressAm: std_ulogic_vector( ldqueuelength - 1 downto 0);
|
variable addressAm: std_ulogic_vector( ldqueuelength - 1 downto 0);
|
variable uaddressAm: unsigned( ldqueuelength - 1 downto 0);
|
variable uaddressAm: unsigned( ldqueuelength - 1 downto 0);
|
variable datumAm: std_ulogic_vector( AmOutBuff'range);
|
variable datumAm: std_ulogic_vector( AmOutBuff'range);
|
variable wAm: std_ulogic;
|
variable wAm: std_ulogic;
|
begin
|
begin
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
if nReset /= '1' then
|
if nReset /= '1' then
|
del <= 15;
|
del <= 15;
|
statequeue <= queuestart;
|
statequeue <= queuestart;
|
queuedone <= '0';
|
queuedone <= '0';
|
interrupt <= '0';
|
interrupt <= '0';
|
accdone <= '0';
|
accdone <= '0';
|
preempted <= '0';
|
preempted <= '0';
|
firstA1 <= ( others => '0');
|
firstA1 <= ( others => '0');
|
A1Outaddr <= ( others => '0');
|
A1Outaddr <= ( others => '0');
|
lastA1 <= ( others => '0');
|
lastA1 <= ( others => '0');
|
counterA1 <= ( others => '0');
|
counterA1 <= ( others => '0');
|
firstAm <= ( others => '0');
|
firstAm <= ( others => '0');
|
AmOutaddr <= ( others => '0');
|
AmOutaddr <= ( others => '0');
|
lastAm <= ( others => '0');
|
lastAm <= ( others => '0');
|
counterAm <= ( others => '0');
|
counterAm <= ( others => '0');
|
getA1 <= '0'; -- NEW
|
getA1 <= '0'; -- NEW
|
getAm <= '0'; -- NEW
|
getAm <= '0'; -- NEW
|
removeA1 <= '0'; -- NEW
|
removeA1 <= '0'; -- NEW
|
removeAm <= '0'; -- NEW
|
removeAm <= '0'; -- NEW
|
putA1 <= '0'; -- NEW
|
putA1 <= '0'; -- NEW
|
putAm <= '0'; -- NEW
|
putAm <= '0'; -- NEW
|
serviced <= '0';
|
serviced <= '0';
|
else
|
else
|
hi := interrupt;
|
hi := interrupt;
|
acc := accdone or doneh;
|
acc := accdone or doneh;
|
|
|
diff := firstA1 - unsigned( RecBuff.FiFoAddr);
|
diff := firstA1 - unsigned( RecBuff.FiFoAddr);
|
|
|
case statequeue is
|
case statequeue is
|
when queuestart =>
|
when queuestart =>
|
getA1 <= '0';
|
getA1 <= '0';
|
|
|
if enablequeue = '1' then
|
if enablequeue = '1' then
|
if found /= 15 then
|
if found /= 15 then
|
if RecBuff.Am = '1' or -- in Am
|
if RecBuff.Am = '1' or -- in Am
|
( RecBuff.Am = '0' and diff( diff'high) = '0') then -- in lower half of A1
|
( RecBuff.Am = '0' and diff( diff'high) = '0') then -- in lower half of A1
|
queuedone <= '1';
|
queuedone <= '1';
|
newFiFoAddr <= RecBuff.FiFoAddr;
|
newFiFoAddr <= RecBuff.FiFoAddr;
|
newAm <= RecBuff.Am;
|
newAm <= RecBuff.Am;
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
elsif fullAm = '1' then
|
elsif fullAm = '1' then
|
-- Am full
|
-- Am full
|
if AmOut.valid = '1' then
|
if AmOut.valid = '1' then
|
del <= to_integer( AmOut.way);
|
del <= to_integer( AmOut.way);
|
toFlush <= AmOut.word;
|
toFlush <= AmOut.word;
|
getAm <= '1';
|
getAm <= '1';
|
hi := '1';
|
hi := '1';
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
end if;
|
end if;
|
else
|
else
|
AmIn.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
|
AmIn.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
|
AmIn.way <= std_ulogic_vector(to_unsigned( found, ldways + 1));
|
AmIn.way <= std_ulogic_vector(to_unsigned( found, ldways + 1));
|
AmIn.valid <= '1';
|
AmIn.valid <= '1';
|
putAm <= '1';
|
putAm <= '1';
|
A1Inaddr <= RecBuff.FiFoAddr;
|
A1Inaddr <= RecBuff.FiFoAddr;
|
removeA1 <= '1';
|
removeA1 <= '1';
|
statequeue <= queuewaitAm1;
|
statequeue <= queuewaitAm1;
|
end if;
|
end if;
|
elsif free /= 15 then
|
elsif free /= 15 then
|
if fullA1 = '1' or (isfull = '1' and emptyA1 = '0' and serviced = '0') then
|
if fullA1 = '1' or (isfull = '1' and emptyA1 = '0' and serviced = '0') then
|
-- remove last entry from A1
|
-- remove last entry from A1
|
if A1Out.valid = '1' then
|
if A1Out.valid = '1' then
|
del <= to_integer( A1Out.way);
|
del <= to_integer( A1Out.way);
|
toFlush <= A1Out.word;
|
toFlush <= A1Out.word;
|
getA1 <= '1';
|
getA1 <= '1';
|
hi := '1';
|
hi := '1';
|
serviced <= '1';
|
serviced <= '1';
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
end if;
|
end if;
|
elsif emptyAm = '0' and isfull = '1' and serviced = '0' then
|
elsif emptyAm = '0' and isfull = '1' and serviced = '0' then
|
-- remove last entry from Am
|
-- remove last entry from Am
|
if AmOut.valid = '1' then
|
if AmOut.valid = '1' then
|
del <= to_integer( AmOut.way);
|
del <= to_integer( AmOut.way);
|
toFlush <= AmOut.word;
|
toFlush <= AmOut.word;
|
getAm <= '1';
|
getAm <= '1';
|
hi := '1';
|
hi := '1';
|
serviced <= '1';
|
serviced <= '1';
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
end if;
|
end if;
|
else
|
else
|
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
|
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
|
A1In.way <= std_ulogic_vector(to_unsigned( free, ldways + 1));
|
A1In.way <= std_ulogic_vector(to_unsigned( free, ldways + 1));
|
A1In.valid <= '1';
|
A1In.valid <= '1';
|
putA1 <= '1';
|
putA1 <= '1';
|
serviced <= '0';
|
serviced <= '0';
|
statequeue <= queuewaitA11;
|
statequeue <= queuewaitA11;
|
end if;
|
end if;
|
elsif elim /= 15 then
|
elsif elim /= 15 then
|
if fullA1 = '1' then
|
if fullA1 = '1' then
|
if A1Out.valid = '1' then
|
if A1Out.valid = '1' then
|
if not ( to_integer( A1Out.way) = elim and
|
if not ( to_integer( A1Out.way) = elim and
|
A1Out.word = AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords)) then
|
A1Out.word = AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords)) then
|
del <= to_integer( A1Out.way);
|
del <= to_integer( A1Out.way);
|
toFlush <= A1Out.word;
|
toFlush <= A1Out.word;
|
statequeue <= queueelim;
|
statequeue <= queueelim;
|
end if;
|
end if;
|
|
|
getA1 <= '1';
|
getA1 <= '1';
|
end if;
|
end if;
|
else
|
else
|
if getA1 = '1' then
|
if getA1 = '1' then
|
preempted <= '1';
|
preempted <= '1';
|
end if;
|
end if;
|
getA1 <= '0'; -- NEW, inserted the only bug!!!!!!!!!!!!!!
|
getA1 <= '0'; -- NEW, inserted the only bug!!!!!!!!!!!!!!
|
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
|
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords);
|
A1In.way <= std_ulogic_vector(to_unsigned( elim, ldways + 1));
|
A1In.way <= std_ulogic_vector(to_unsigned( elim, ldways + 1));
|
A1In.valid <= '1';
|
A1In.valid <= '1';
|
putA1 <= '1';
|
putA1 <= '1';
|
statequeue <= queueelim;
|
statequeue <= queueelim;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
when queuewait =>
|
when queuewait =>
|
removeA1 <= '0';
|
removeA1 <= '0';
|
removeAm <= '0';
|
removeAm <= '0';
|
getAm <= '0';
|
getAm <= '0';
|
getA1 <= '0';
|
getA1 <= '0';
|
queuedone <= '0';
|
queuedone <= '0';
|
|
|
if hi = '1' then
|
if hi = '1' then
|
hi := '0';
|
hi := '0';
|
statequeue <= queuestart;
|
statequeue <= queuestart;
|
elsif acc = '1' then
|
elsif acc = '1' then
|
acc := '0';
|
acc := '0';
|
del <= 15;
|
del <= 15;
|
statequeue <= queuestart;
|
statequeue <= queuestart;
|
end if;
|
end if;
|
when queuewaitAm1 =>
|
when queuewaitAm1 =>
|
putAm <= '0';
|
putAm <= '0';
|
removeA1 <= '0';
|
removeA1 <= '0';
|
statequeue <= queuewaitAm2;
|
statequeue <= queuewaitAm2;
|
when queuewaitAm2 =>
|
when queuewaitAm2 =>
|
newFiFoAddr <= AmOutAddr;
|
newFiFoAddr <= AmOutAddr;
|
newAm <= '1';
|
newAm <= '1';
|
queuedone <= '1';
|
queuedone <= '1';
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
when queuewaitA11 =>
|
when queuewaitA11 =>
|
putA1 <= '0';
|
putA1 <= '0';
|
statequeue <= queuewaitA12;
|
statequeue <= queuewaitA12;
|
when queuewaitA12 =>
|
when queuewaitA12 =>
|
newFiFoAddr <= A1OutAddr;
|
newFiFoAddr <= A1OutAddr;
|
newAm <= '0';
|
newAm <= '0';
|
removeA1 <= '0';
|
removeA1 <= '0';
|
removeAm <= '0';
|
removeAm <= '0';
|
queuedone <= '1';
|
queuedone <= '1';
|
preempted <= '0';
|
preempted <= '0';
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
when queueelim =>
|
when queueelim =>
|
putA1 <= '0';
|
putA1 <= '0';
|
getA1 <= '0';
|
getA1 <= '0';
|
|
|
if RecBuff.Am = '1' and preempted = '0' then
|
if RecBuff.Am = '1' and preempted = '0' then
|
AmInAddr <= RecBuff.FiFoAddr;
|
AmInAddr <= RecBuff.FiFoAddr;
|
removeAm <= '1';
|
removeAm <= '1';
|
elsif preempted = '0' then
|
elsif preempted = '0' then
|
A1InAddr <= RecBuff.FiFoAddr;
|
A1InAddr <= RecBuff.FiFoAddr;
|
removeA1 <= '1';
|
removeA1 <= '1';
|
end if;
|
end if;
|
|
|
if getA1 = '1' then
|
if getA1 = '1' then
|
hi := '1';
|
hi := '1';
|
preempted <= '1';
|
preempted <= '1';
|
statequeue <= queuewait;
|
statequeue <= queuewait;
|
else
|
else
|
statequeue <= queuewaitA12;
|
statequeue <= queuewaitA12;
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
interrupt <= hi;
|
interrupt <= hi;
|
accdone <= acc;
|
accdone <= acc;
|
|
|
if putA1 = '1' or removeA1 = '1' then
|
if putA1 = '1' or removeA1 = '1' then
|
if removeA1 = '0' then
|
if removeA1 = '0' then
|
addressA1 := std_ulogic_vector( firstA1);
|
addressA1 := std_ulogic_vector( firstA1);
|
datumA1 := A1In.valid & A1In.way & A1In.Word;
|
datumA1 := A1In.valid & A1In.way & A1In.Word;
|
firstA1 <= firstA1 + 1;
|
firstA1 <= firstA1 + 1;
|
counterA1 <= counterA1 + 1;
|
counterA1 <= counterA1 + 1;
|
A1Outaddr <= std_ulogic_vector( firstA1);
|
A1Outaddr <= std_ulogic_vector( firstA1);
|
else
|
else
|
addressA1 := A1Inaddr( addressA1'range);
|
addressA1 := A1Inaddr( addressA1'range);
|
datumA1 := ( others => '0');
|
datumA1 := ( others => '0');
|
end if;
|
end if;
|
wA1 := '1';
|
wA1 := '1';
|
else
|
else
|
uaddressA1 := lastA1;
|
uaddressA1 := lastA1;
|
if (getA1 = '1' or A1Out.valid = '0') and counterA1 /= 0 then
|
if (getA1 = '1' or A1Out.valid = '0') and counterA1 /= 0 then
|
counterA1 <= counterA1 - 1;
|
counterA1 <= counterA1 - 1;
|
uaddressA1 := uaddressA1 + 1;
|
uaddressA1 := uaddressA1 + 1;
|
end if;
|
end if;
|
lastA1 <= uaddressA1;
|
lastA1 <= uaddressA1;
|
addressA1 := std_ulogic_vector( uaddressA1);
|
addressA1 := std_ulogic_vector( uaddressA1);
|
wA1 := '0';
|
wA1 := '0';
|
end if;
|
end if;
|
|
|
if wA1 = '1' then
|
if wA1 = '1' then
|
ramA1( to_integer( addressA1)) <= datumA1;
|
ramA1( to_integer( addressA1)) <= datumA1;
|
else
|
else
|
A1OutBuff := ramA1( to_integer( addressA1));
|
A1OutBuff := ramA1( to_integer( addressA1));
|
|
|
A1Out.Word <= A1OutBuff( blocksizeld - 1 downto 0);
|
A1Out.Word <= A1OutBuff( blocksizeld - 1 downto 0);
|
A1Out.way <= A1OutBuff( blocksizeld + ldways downto blocksizeld);
|
A1Out.way <= A1OutBuff( blocksizeld + ldways downto blocksizeld);
|
A1Out.valid <= A1OutBuff( blocksizeld + ldways + 1);
|
A1Out.valid <= A1OutBuff( blocksizeld + ldways + 1);
|
end if;
|
end if;
|
|
|
if putAm = '1' or removeAm = '1' then
|
if putAm = '1' or removeAm = '1' then
|
if removeAm = '0' then
|
if removeAm = '0' then
|
addressAm := std_ulogic_vector( firstAm);
|
addressAm := std_ulogic_vector( firstAm);
|
datumAm := AmIn.valid & AmIn.way & AmIn.Word;
|
datumAm := AmIn.valid & AmIn.way & AmIn.Word;
|
firstAm <= firstAm + 1;
|
firstAm <= firstAm + 1;
|
counterAm <= counterAm + 1;
|
counterAm <= counterAm + 1;
|
AmOutaddr <= std_ulogic_vector( firstAm);
|
AmOutaddr <= std_ulogic_vector( firstAm);
|
else
|
else
|
addressAm := AmInaddr( addressAm'range);
|
addressAm := AmInaddr( addressAm'range);
|
datumAm := ( others => '0');
|
datumAm := ( others => '0');
|
end if;
|
end if;
|
wAm := '1';
|
wAm := '1';
|
else
|
else
|
uaddressAm := lastAm;
|
uaddressAm := lastAm;
|
if (getAm = '1' or AmOut.valid = '0') and counterAm /= 0 then
|
if (getAm = '1' or AmOut.valid = '0') and counterAm /= 0 then
|
counterAm <= counterAm - 1;
|
counterAm <= counterAm - 1;
|
uaddressAm := uaddressAm + 1;
|
uaddressAm := uaddressAm + 1;
|
end if;
|
end if;
|
lastAm <= uaddressAm;
|
lastAm <= uaddressAm;
|
addressAm := std_ulogic_vector( uaddressAm);
|
addressAm := std_ulogic_vector( uaddressAm);
|
wAm := '0';
|
wAm := '0';
|
end if;
|
end if;
|
|
|
if wAm = '1' then
|
if wAm = '1' then
|
ramAm( to_integer( addressAm)) <= datumAm;
|
ramAm( to_integer( addressAm)) <= datumAm;
|
else
|
else
|
AmOutBuff := ramAm( to_integer( addressAm));
|
AmOutBuff := ramAm( to_integer( addressAm));
|
|
|
AmOut.Word <= AmOutBuff( blocksizeld - 1 downto 0);
|
AmOut.Word <= AmOutBuff( blocksizeld - 1 downto 0);
|
AmOut.way <= AmOutBuff( blocksizeld + ldways downto blocksizeld);
|
AmOut.way <= AmOutBuff( blocksizeld + ldways downto blocksizeld);
|
AmOut.valid <= AmOutBuff( blocksizeld + ldways + 1);
|
AmOut.valid <= AmOutBuff( blocksizeld + ldways + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process queues;
|
end process queues;
|
|
|
fullA1 <= counterA1( counterA1'high);
|
fullA1 <= counterA1( counterA1'high);
|
emptyA1 <= '1' when counterA1 = 0 else '0';
|
emptyA1 <= '1' when counterA1 = 0 else '0';
|
|
|
fullAm <= counterAm( counterAm'high);
|
fullAm <= counterAm( counterAm'high);
|
emptyAm <= '1' when counterAm = 0 else '0';
|
emptyAm <= '1' when counterAm = 0 else '0';
|
|
|
end Rtl;
|
end Rtl;
|
|
|
|
|
